Connect with us

SRAM Power Consumption

Discussion in 'Electronic Design' started by Patrick, Apr 30, 2007.

Scroll to continue with content
  1. Patrick

    Patrick Guest

    Hi

    I have got an SRAM Cache with 512 Cache Lines each 16 Bytes long with
    associativity of 1.
    For storing one bit I use a 6T RAM Cell. I used HotLeakage to estimate
    the power consumption for an
    0.07 process. The leakage cell_data for one 6T RAM Cell is calculated
    by the leakage of an nmos plus the leakage of
    a pmos transistor. The bitline leakage bitline_data for one cell is
    the leakage of an nmos transistor. This value has then be multiplied
    by the number of ports ->

    power_leakage_cache = (cell_leakage + bitline_leakage *
    number_of_ports) * 16(Bytes per Line) * 8 (Bits per Bytes) * 512
    (cache Lines in total)

    In other words, if all the cache would contain useful data in each
    line I get the following results:

    tagarray_power (W): 0.0021203
    datarray_power (W): 0.00512072

    In other words, one cache line consumes 10nW. Can this be possible or
    did I miss something?

    Cheers!
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-