SRAM integration: tristate I/O

[sungchoiok]

Hello. I need some help with configuring tristate input/outputs for SRAMs (or any other ICs for that matter). This is such a noob question that I don't think I even belong here, but I would really appreciate any kind alleviation:


This is a hypothetical SRAM. It has two address inputs and one-bit I/O bus. Now, I understand how to use pull-up resistors to send signals to the input pins, such as the /WE, /OS, /CS, A1, and A2 (as shown on the first thumbnail), but I do not understand how to configure my circuitry so that the I/O bus gets input signals, but also output a signal when it is requested to.


I have drawn my "possible" solution on the second thumbnail... please don't laugh at me.




thank you in advance.

 

[(*steve*)]

The I/O connects directly to a data bus.

When the data bus has data on it, the I/O pin is either an input or high impedance (the third state).

When the data is to be read from the device, the I/O pin is set to be an output after all other devices on the bus have been set to either inputs or high impedance.