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SR Latch with NOR

Discussion in 'Electronic Basics' started by David Taylor, Jan 6, 2004.

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  1. David Taylor

    David Taylor Guest
    I'll refer to Q and Q' as Q and QN, as they are different outputs and
    one is not necessarily the complement of the other.

    I get that R means reset and Set means set.
    But I don't understand the meaning of the second output QN. Is it
    just an implementaion thing required only to ensure Q has the right
    Would QN be discarded, for example the circuit for Prog+ and Prog- on
    a remote control or the circuit for a burgler alarm just gives 1

    More importantly, if I feed in previous values of Q and QN, I don't
    get the right result, I should find that
    when R=1 S=0 then Q should equal 0
    when R=0 S=1 then Q should equal 1
    And I'd have thought the previous values of Q and QN are irrelevant.

    I'll describe the results i'm getting-
    suppose R=0 S=1 and the previous outputs now going in are Q=0 QN=1
    I expect a result of Q=1 as R means reset, and S means set.

    In the top NOR gate, (R NOR QN)=(0 NOR 1)= 0 so new Q=0
    This is not right, Q should be Set, Q should = 1.

    Im the bottom NOR gate, new QN=0.

    If I had not fed in previous inputs and just said that as R=0 NOR
    can't be evaluated yet. S=1 so QN=0 Feeding in R with the new QN, R
    NOR QN gives 1 so Q=1. If I do that, then I get the right result.

    Another thing i don't understand is that I keep reading that when S=0
    and R=0 then Q and QN should retain their original values. I find
    this only to be true when Q=0 and QN=1 or Q=1 and QN=0. Clearly,
    when Q=0 and QN=0, you feed in
    R NOR QN that's 0 NOR 0 =1 so Q=1
    you feed in that old Q
    S NOR Q so QN=1
    Clearly Q and QN have flipped, and not retained their original values.
    Similarly, with R=0 S=0 and Q=1 QN=1, the NOR gates see the 1s coming
    in, evaluate to 0, and so Q=0 QN=0, so they've flipped too.
    Definitely not retainig their values as they should be.

    An additional problem I have, is that the definition of sequential
    logic circuit "one whose output depends not only on its inputs but
    also on its past sequence of inputs" Surely this NOR SR latch is
    feeding in past outputs rather than past inputs. I don't see any old
    Rs and Ss going in, only an old Q and QN.

    Thanks in advance
  2. David Taylor

    David Taylor Guest

    Gajski on P.213 implies that Q is input not QN, and also, the input Q
    only has an effect on the output Q when S=0 and R=0. Also, when S=1
    and R=1
    it is something designers try to avoid as it doesn't make sense to
    reset and set the latch simultaneously. This clears everything up,
    leaving 2 question of minor significance.

    1 How electronically does it work out that Q is inputted and QN isn't?
    If you look at the circuit diagram, it clearly shows QN inputted.

    2 "Sequential logic circuit – outputs depend on its inputs and past
    sequence of inputs. " (e.g. prog up and down on a remote control)
    Wakerly p.529

    note: A far easier to understand boolean algebra expression is given
    in Gajski p.226 Q(next)=S+R'Q Q(next) meaning new Q (the Q
    outputted), and, Q meaning old Q (the Q inputted).
  3. This is a very basic logic building block treated in every book a ever saw
    on logic systems. You call it a latch. It's often called "trigger" or
    "flipflop" as well but it has no use to start a discussion about that.
    The circuit will not function without it. There may be or not be a use for
    QN outside this circuit but inside you cannot do without it.

    It may be hidden in a box or even in a chip but this circuit requires QN.
    You're mixing logic with levels. The outputs are inverted with respect to
    the inputs.
    As I said the outputs are inverted. You will have the "correct" results by
    inverting them again using inverters between the outputs of the gates and
    the external signals. In a practical situation you will simply exchange Q
    and QN.
    Q is complementary to QN by definition. They both remember whether the set
    or the reset has been "true" the last time. (Although the level has
    inverted.) You can make both Q and QN low by driving both inputs high but
    that is a forbidden input combination. When this happens the circuit losts
    his memory. It is up to the designer to prevent this situation. As an
    alternative you can design an RS-element with an overriding set or an
    overriding reset.
    The Qs *are* the old Rs and Ss. The output *does* not depend on the input
    only. Q reminds which of the inputs has been true the last time even if the
    signal itself has disappeared already. It's all a simple memory element like
    this *can* do. It's up to the designer once more to use this type of
    elements as building blocks for more complated sequential machines.
    You're welcome.

  4. Steve

    Steve Guest

    I think this examination of an SR flip-flop is akin to using a tea
    spoon to dig the channel tunnel.

    Or perhaps it's like using a 200 tonne drag line excavator to repair a
    divot on a golf green... I'm not sure which is more appropriate.

    Either way, such a detailed examination of an SR flip flop would seem
    to me to be a waste of time. Just accept that it works, build one if
    you have to satisfy your curiosity; then get on with more important

  5. John Fields

    John Fields Guest

    Neither one of them is an example of anything which has anything to do
    with explaining regeneration or memory, so they're both stupid
    A worse waste of time is your complaining about something which,
    obviously, has nothing to do with you. This is sci.electronics.basics,
    and a subject which may seem mundane to you may be conceptually
    difficult for someone else. This is just the right place for them to
    ask whatever they want to without having to worry about whether someone
    else thinks it's stupid, or a waste of time, or whatever.
  6. Doggy,

    You're on the wrong trail. The best way to learn complex digital circuits is
    a good understanding of the basic blocks. In this particular case the OP
    understands the inner working of the circuit well enough. He was only
    confused as it did not function like he expected. Expectations based on
    general statements about logic circuits that seemed to be contraditionary to
    his experience. (Somehow he's right too. The terminology of logic people is
    not always as logic as it should be.) I'm not a fortune-teller but I expect
    him to become a great logic designer. And as I love the profession I'll try
    to answer any fair question, especially newbees questions. This group is
    supposed to exist for it.

  7. Steve

    Steve Guest

    I wasn't referring to regeneration or memory in my analogies, I was
    referring to the amount of effort going into understanding the

    Besides, I thought it was funny... get off your high horse and loosen
    I wasn't complaining.
    WTF? This is Usenet. Of course it has nothing to do with me, just as
    it technically has nothing to do with you. You chose to post your
    opinion, as did I.
    Really? Sheesh, I thought I was in the Bahamas!
    You're reading things into my post. I never implied that it was


  8. Steve

    Steve Guest

    The best way to learn complex digital circuits is a good
    understanding of the basic blocks.

    I repair digital video equipment, and in four years of my current job
    such a thorough understanding of an SR flip flop built from NAND gates
    has NEVER been needed.

    I appreciate that it's good to know, but it seemed like the OP was
    delving into it in immense detail. From a quick look around the
    website given, this effort was disproportionate to the amount of
    attention paid to the device in the course.

    I wasn't saying "don't bother learning this", I was suggesting that
    sometimes you can try too hard to understand that which is relatively
    unimportant. You can end up chasing your tail for days over a trivial
    I was trying to express that perhaps the OP may be spending precious
    time and effort chasing their tail when there are far more exciting
    and important things about logic circuits to learn.

    In the end, the OP said:
    "...S=1 and R=1 is something designers try to avoid as it doesn't make
    sense to reset and set the latch simultaneously. This clears
    everything up..."

    This is the easy way out I'm talking about. Forget trying to analyse
    what happens when you DO set and reset at the same time, just accept
    that it's unpredictable and should be avoided.

    There's a lot of reading between the lines going on in this thread...

  10. George

    George Guest

    The past values are why this circuit holds memory, the main function
    of a latch.
    You need to give the circuit time to stabilize. You do not just accept
    the initial outputs from the latch, you give it time to stabilize.
    Take your R=0, S=1, and your new outputs Q and QN =0. Put those
    through the circuit a second time, you get Q=1 and QN=0. This is will
    stay that way until the inputs change. This is the correct outputs.
    This circuit has no clock so the NOR calculations will keep happening
    until they stabilize. The reason you never input S=1 R=1 is that there
    is no way of predicting what the circuit will stabilize at in most
    sequences, or that it will stabilize at an unacceptable combination.
    As other posts have said, you should never have Q and QN equal each
    other so that is not a problem that matters.
    The outputs are based on past inputs. Thus, the fact that you include
    past outputs in the circuit automatically means you include past
    inputs. Hence a latch is a sequential.
  11. John Fields

    John Fields Guest

    I'm quite aware of what you _weren't_ referring to.

    If the OP wanted to spend the rest of his life, and a fortune, trying to
    understand the circuit then that's his business and good for him. When
    you come along with your destructive criticisn and, instead of offering
    an explanation which might clarify things for him, tell him that he's
    wasting his life, that's _not_ a good thing.
    What about it did you think was funny?

    On the one hand you present a scenario where a herculean task is being
    attempted with trivial resources (the OP is too stupid to be able to
    understand the magnitude of the task at hand) and on the other you
    present a scenario where a trivial task is being performed with
    herculean resources. (The OP is too stupid to understand the magnitude
    of the task at hand)

    Thank you, but I'd rather ride than crawl along down there with the
    likes of you.
    Webster disagrees with you, but don't bother to look it up. Just take
    my word for it.
    By 'not having anything to do with you' I was referring to your
    failure/inability to address the technical content of the OP's post. My
    post, while admittedly off-topic, was in response to the content of your
    post (which I found objectionable) and therefore became interesting to
    me and therefore had spmething to do with me.

    Yet, in another post, you said:

    "I was trying to express that perhaps the OP may be spending precious
    time and effort chasing their tail when there are far more exciting
    and important things about logic circuits to learn."
  12. David Taylor

    David Taylor Guest

    This is a very basic logic building block treated in every book a ever saw
    but all good books state that latches don't have clocks, and flip
    flops do. Good books and good lecture slides state that bad books and
    bad slides call latches flip flops. So I don't call a latch a flip
    flop. I won't cite examples as it's not relevant to the thread.

    Isn't the logic the meaning of the levels, it's what the levels
    represent. HIGH represents 1. LOW represents 0. So If I say 0 and 1,
    then i'm looking at the meaning. If I say HIGH and LOW, then I'm
    looking at the implementation. I don't see how it's wrong to say
    R=1 S=0 e.t.c. Truth tables do it, books do it when they show truth
    tables, what's the problem with it?

    From what i've read - inverters are used in the NAND latch for correct
    results, not in the NOR latch.
    Q and QN need not be exchanged in the NOR latch.
    My problem, is that if I put Q and QN into the gates first, I get
    one result, and if I put R and S in first, I get another result (the
    right one). Do R and S have to reach the gates before Q and QN in
    order for the circuit to work? That's the problem I'm having.

    The older problem of R&S=1 and oscillations is now resolved to a level
    i'm comfortable with.

  13. David Taylor

    David Taylor Guest

    I'll describe the results i'm getting-

    I had no idea that R=0 S=1 could ever be unstable initially, as none
    of my books treat latches in such detail.
    It all makes sense now.
    You've sorted it out.
    many thanks.
  14. I know. Just wrote it down for your information.
    It's a matter of theory. This circuit is supposed to remember the last
    action. If the last action was set (a positive pulse on S) it is remembered
    by keeping Q low. So the output is inverted with respect to the last action.
    You can say that Q remembers the last reset correctly. But by convention the
    Q is related to the set, not to the reset.

    Theoretical logic knows "true" and "false" also named "1" and "0"
    respectively. Practical circuits knows "high" and "low" also named "on" or
    "off". Most of the times "true" and "high" are considered to be the same.
    This is called positive logic. But there's no reason to call "low" "true".
    No surprise that's called negative logic. Then there is mixed logic as well.
    In practical circuits you often see the term "active low" for inputs as well
    as for outputs. That's where the positive logic is not so logical as the
    active or "true" level is "low". In alphabetic terms there's often an "N"
    placed behind it or a "/" for it. There are other notations as well. There's
    no problem with it as long as you talk about simple gates. But you can run
    into a lot of confusion when you have to analyze or design more complicated
    digital circuits. You'll find it out for yourself soon enough.
    NAND latches can be considered to have active low inputs, where NOR latches
    can be considered to have active low outputs. They both need inverters if
    you want to keep positive logic only. As I said nobody cares in practical
    Q and QN are outputs. They are in a kind of a feedback loop but nevertheless
    you cannot separate them from the inputs of the gates. You also cannot
    expect a digital circuit that has undifined inputs to have well defined
    outputs. Theoretically the ouput of a gate follows the input immediately.
    Practical gates have a delay time, that's the time required to stabilize the
    new output as a reaction on an input change. But in both situations you
    cannot put Q and QN into the gates but by controlling set and/or reset. The
    only exception is at power on, but even then it gets some value somehow and
    you can't be sure whether it will be high or low. That's why the state of
    this circuit is not defined after power on. You have to initialize it
    somehow. Which requires extra hardware.

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