spice Ver4 model - sync rec mosfet - body diode charge

[legg]

Some of you may be familiar with issues around self-synchronizing
normally-off
mosfet rectifier control. This is basically an attempt to get mosfets
to behave
as 'ideal' rectifiers, using the simplest control method - a linear
negative Vds
regulation in the third quadrant.

Apart from the issue of accurately modeling the integrated version of
a controller, the behavior of the mosfet body diode is creating
modeling anomalies.

Drain currents flowing as the drain voltage rises at turn-off do not
seem to be related to current levels experienced by the mosfet
parasitic diode - rather they scale to current flowing through the
enhanced mosfet channel at turn-off - a structure that is supposed to
be storage-charge immune.


web page with links to swcadIV files and pdf format are available at:

http://www.magma.ca/~legg/20_Years/1994/1994h.html

images of simulation traces and representative schematic at:

http://www.magma.ca/~legg/SR5/SR5a004on-Lstep.jpg
http://www.magma.ca/~legg/SR5/SR5a004off-Lstep.jpg
http://www.magma.ca/~legg/SR5/SR5a004off-sch.jpg

Any ideas, please comment.

RL

 

[legg]

On Thu, 06 Jan 2011 13:31:19 -0700, Jim Thompson

Circuit is too complicated

...Jim Thompson

I'm too clued out to even know if you're joking, Jim.

Doubt that mfrs' foundry models will function, without mucho more
extra bits, if only to get functional gain. I'll never see 6nSec
turn-off; that's for sure.

RL

 

[legg]

(1) You need to make sure that the CMOS model version supports
including the body diode

(2) And then whether the manufacturer characterized and included that
effect in the model

...Jim Thompson

Just seeing the drain voltage clamp tells me that there's a diode
function present, but the part must use some kind of default, as the
only parameters listed are the usual VDMOS descriptors in SWCADIV.
Same thing with other 'vendor' part models suplied out of the box.

It's not capacitive, not even non-linear cap, and it doesn't have a
diode's form either.

RL

 

[legg]

Partially ;-) Too many parts in your below-ground sensing.

There's only one npn collector (one that would have to be in a buried
well for isolation) acting as an emitter in inverted mode. The
resistor is the crude voltage regulation adjustment at the moment.

Nope. I just looked up a 2N7002... Level=3 :-(

What I have done is take IC foundry models and scaled them to somewhat
match discrete devices. But it's tedious work.

...Jim Thompson

What I'd need to do is to make the foundry models work, assuming
they're the best representations of what the foundry can can actually
produce.

RL

 

[legg]

What would be nice to run across would be a tool to take the DC stuff
from Level=3 and convert to Level=7, then you could tweak in the rest
of the stuff, like body diode, gate charge and below-threshold
behavior.

...Jim Thompson

This image is a comparison between storage charge in a conventional
ultrafast rectifier and the mosfet at roughly the same current levels.
I've left the gate driver and mosfet nodes in place, just to give an
idea of what they do 'open-loop'. ( Funny seeing a turn-on gate
voltage step, in the other condition not shown here - in response to
near-zero-voltage disconnected drain charge transfer..... and where
this circuit gets >20A for the gate drive turn-off.....but lets not
get distracted.)

http://www.magma.ca/~legg/SR5/SR5a004off-mur640.jpg

In the conventional rectifier, stored charge is probably accurately
tailored to reflect the current at the time of voltage reversal.
The current shape is probably accurate enough for the circuits we hang
around with.

The behavior of stored charge under the influence of low voltage mos
drain behavior is probably something that isn't very well documented.

From memory, all I recall is some speculation that package inductances
may be influential when you're talking multi-amps, millivolts and
microseconds - this in relation to physically paralleled mos and
schottky structures.

RL

 

[legg]

legg wrote:

That's a pretty nice looking snap on that MUR640, at least at this
resolution. Must make for fun EMC testing!

Cheers

Phil Hobbs

This is just the output of a simulation.

I don't have a scope or a current transformer with that kind of
bandwidth. Conventional reverse recovery current is depicted with
finite and constant di/dt as an 'experimental' control, with variously
shaped reductions and oscillations after the peak.

The mosfet version is a haversine, the origins of which are part of
the question here.

RL

 

[legg]

That's a pretty nice looking snap on that MUR640, at least at this
resolution. Must make for fun EMC testing!

Cheers

Phil Hobbs

Another thing about these waveforms:

In conventional reverse recovery, the voltage across the
reverse-biased diode cannot rise until after the moment of peak
reverse current. This is becaused the rectifier does not block until
all charge is evacuated. Neither of the illustrated waveforms follows
that convention.

For the mos rectifier simulation the voltage on the drain is seen to
rise above zero as the current passes through zero.

For the ultrafast simulation, the voltage slowly approaches zero as
the current reduces and reverses, passing through zero when the
reverse current is roughly half the final peak value. The 2V apearing
on the diode at the time of 'snap-off' would not likely be significant
in a simulation of switching loss, as the bulk of the energy loss is
still delivered to the switch.

RL

 

[legg]

Musing over your problem this morning, I note that MOST Power MOSFET
modelers are all over the place with modeling the body diode.

And there are actually two... body-to-source and body-to-drain.

You can't measure the body-to-source one since the body is tied to the
source internally.

But you can measure the body-to-drain diode...

Tie gate to source then curve trace (or point by point)
source-to-drain, obtaining IS for the diode (and RS, if you're
careful).

Make a subcircuit with diodes from body-to-source and body-to-drain,
both of the same IS (and RS) as obtained by your measurement... it's a
good bet that source and drain area are the same, or very close.

If your basic MOS model includes body-to-source and body-to-drain
capacitances, modeling only IS (and RS) should be adequate for your
task, though adding a guestimate of TT might be helpful).

...Jim Thompson

Been doing a bit of reading up on the models presently available in
LTSpice - it seems that this issue has been addessed through a number
of avenues. mosfet models can be spec'ed up to L9. Building a
subcircuit to to the job needed seems to be the approach. Puts me in
the position of having to prove what's needed.

Unfortunately all models of reverse recovery reference the current at
the time of voltage reversal for charge injection levels. The behavior
of stored charge in the body of the enhanced fet body diode isn't
considered.

This isn't a static characteristic, but I guess it can be scoped out
using real parts - will have to be if it's not already covered in the
literature. If there's a moderation or modulation, it should be as
workable in a model as temperature effects, once you have some
pointers.

If charge accumulation isn't avoidable, you'd end up with a low
forward drop fast characteristic, rather than a recovery-free one.

RL

 

[legg]

I don't see that a body diode is any different than any other diode,
if fully characterized... which is the trick.

It appears that the LTSpice mosfet body diode does not model reverse
recovery in any way. Hendrik Jan Zwerver writes that the body diode is
given a forward voltage characteristic and is used to model nonlinear
Cds (Coss) of the fet it's attached to.

http://www.magma.ca/~legg/SR5/LTspice_build_in_VDmos_model.pdf

The following is a comparison of an ultrafast diode and a mosfet with
gate shunted to source through a resistor ( 1R - 10R no effect. 10R
Vgs is plotted n008):

http://www.magma.ca/~legg/SR5/SR5a004off-mur640-fetbody.jpg

I now have no idea where the fet current originates in the sync rec
sim:

http://www.magma.ca/~legg/SR5/SR5a004off-mur640.jpg

RL

 

[Fred Bartoli]

legg a écrit :

It appears that the LTSpice mosfet body diode does not model reverse
recovery in any way. Hendrik Jan Zwerver writes that the body diode is
given a forward voltage characteristic and is used to model nonlinear
Cds (Coss) of the fet it's attached to.

http://www.magma.ca/~legg/SR5/LTspice_build_in_VDmos_model.pdf

The following is a comparison of an ultrafast diode and a mosfet with
gate shunted to source through a resistor ( 1R - 10R no effect. 10R
Vgs is plotted n008):

http://www.magma.ca/~legg/SR5/SR5a004off-mur640-fetbody.jpg

I now have no idea where the fet current originates in the sync rec
sim:

http://www.magma.ca/~legg/SR5/SR5a004off-mur640.jpg

RL

It's not the body diode that lacks reverse recovery modeling. It's the
basic diode model which is totally useless: recovers up to some
predefined time (don't take any recovered charge into account) then it
snaps abruptly.

If you want more or less real reverse recovery, you'd have to build
yourself one into the model.
I have some aimed at soft recovery modeling if you're interested.

 

[legg]

legg a écrit :

It's not the body diode that lacks reverse recovery modeling. It's the
basic diode model which is totally useless: recovers up to some
predefined time (don't take any recovered charge into account) then it
snaps abruptly.

If you want more or less real reverse recovery, you'd have to build
yourself one into the model.
I have some aimed at soft recovery modeling if you're interested.

There is a soft recovery diode in LTSpice, though it's a subcircuit at
the moment. Just look for "Soft_Diode.asc".

Of course I'm interested, but can't be sure that the body diodes
actually existing in the fets being modeled would behave one way or
another, now, without serious characterization.

What do yours do if current flow stops, but reverse voltage isn't
immediately reapplied?

The fact that there wasn't any kind of diode recovery in the fet
wasn't obvious from the controlled gate voltage turn-off sim. I don't
know where the current flowing in the sim fet drain at that time comes
from, now.

RL