Connect with us

spice mos transistor saturation

Discussion in 'Electronic Design' started by [email protected], Jul 18, 2006.

Scroll to continue with content
  1. Guest


    I've been trying some analog IC design but I'm running into difficulty
    with things conceptually ("seeing" what is going on in the circuit) and
    practically (getting something I've made to work, in simulation) - ie.
    moving beyond what I was taught at university.

    Specifically for the latter, I keep running into problems with getting
    FETs to run in saturation. For example, an NMOS cascoded current
    mirror: I've got the two cascoded input transistors on the left with
    drain and gate connected, so no matter what, these will always be in
    saturation. Then, connecting the gates of these biasing transistors to
    the gates of two cascoded output transistors, with the same Vgs, the
    output transistors should operate with the same drain current. But I've
    got an active PMOS load above the current mirror and it is dropping
    about 2.4V (with 2.5V supply rails), leaving only a few mV across the
    drain-source of the cascoded output transistors, so that they operate
    in their linear region instead of in saturation. The input transistors
    have an almost identical load as the output, but as they have their
    gate and drain tied together, they do stay in saturation.

    So I guess my question is: how do I go about stopping the PMOS load
    dropping all my voltage? The PMOS and NMOS transistors have W/L ratios
    such that the PMOS is 1.5 times the NMOS, but changing these ratios
    doesn't seem to have a significant effect on the output NMOS Vds.

    Thanks for any enlightenment!

  2. Jim Thompson

    Jim Thompson Guest

    I suspect you have a current source loaded by a current sink??

    Think about it... it doesn't have a stable operating point unless
    there's some sort of feedback loop.

    ...Jim Thompson
  3. Joerg

    Joerg Guest

    Hello Bill,
    I am not a chip design expert like Jim but how is that PMOS load biased?

    As Chris mentioned a circuit diagram will greatly help here.
  4. Chris Jones

    Chris Jones Guest

    A diagram would be helpful, (in particular the PMOS "active load" that you
    mention). If you can put a diagram on a website or ABSE, then that would
    be good.

Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day