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SPI Configuration

Discussion in 'Electronic Design' started by Sreeram S, Oct 17, 2005.

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  1. Sreeram S

    Sreeram S Guest


    I am trying to interface an MPC5554 procesor with 68HC908 processor
    using SPI ( Serial Peripheral interface). MPC5554 is the Master CPU. I
    have little experience in configuring the SPI in low level. I would like to
    know the following.

    1. What are the factors that I should consider while selecting the Clock
    Polarity and Clock Phase? In my case both Master and Slave CPUs support
    Clock Phase and Clock polarity of 0 and 1.

    2. What are the factors that I should consider while deciding the delay
    between the slave select signal and the first clock edge also the delay
    between the last clock edge and the slave deselection?
    i.e. The delay between Slave select going low and the first clock edge.

    3. What should be the optimum time difference between the transmition of two
    message frames?

    It will be very helpful if somebody can throw some light on this.

    Thanks and Regards,
  2. Rich Grise

    Rich Grise Guest

    As long as they're both the same, it should work regardless, yes.

    And you shouldn't have to worry about that anyway, unless you're
    bit-banging it at one end or the other - don't you just write a
    byte to the SPI transmitter and it takes care of all the timing,
    then when that byte shows up at the receiver, you get an interrupt,

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