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SMPS noise

Discussion in 'Electronic Design' started by QQ, Feb 24, 2005.

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  1. QQ

    QQ Guest

    Hi,

    I am experiencing a problem with some DC/DC non-isolated buck
    converters using LM2743, on a otherwise digital board (16 layer) and am
    grateful for any help offered.

    I have designed a number of voltage mode DC/DC converters on a board.
    They are split into - a group of 3 (G3) that are close to one another
    and another group of 5 (G5) which are close to one another. They all
    run off a 12V power rail. All regulators are running at 350 KHz
    switching frequency approximately (the resistor that sets this does not
    gaurentee that the frequency will be 'exactly' set).

    The problem is - one of the regulators in G3 and one of the regulators
    on G5 have a certain amount of low frequency noise (50mV max -
    periodic, 4 KHz freq , but not sinusoidal, rather irregular shaped)
    that in turn has the normal switching noise (15mV) of the buck topology
    riding on it - as measured with a BNC cable probe, on the output caps -
    a 'null test' was performed too and I am quite confident that the noise
    is real.
    During all tests the noisy G3 rail is isolated from everything else on
    the board. It had a second noise filter inductor due to an ultra low
    noise requirement, which I removed for the testing. Not looked at the
    noisy G5 rail as of yet. The noisy G3 rail is 1.2V and the one
    immediately next to it is 1.8V. The noisy G5 rail is 5V.

    - When the other regulators in G3 are turned off, the low freq noise on
    the noisy regulator in G3 is reduced and changes shape but does not go
    away altogether.
    - When all other regulators on board are switched off the LF noise on
    the noisy regulator in G3 goes away altogether.
    - If I change the freq of the noisy G3 regulator to 300 kHz or 400 KHz
    while keeping switch freq on the other regulators 350 KHz as before, LF
    noise on the noisy G3 regulator goes away
    - If I change the freq of all regs to 300KHz the noise reappears on the
    noisy G3 regulator.
    - I tried lifting the SGND (connected by a thin net to PGND as of
    now)pin of the chip and connecting it to another ground point - this
    doesn't help. I tried air wiring the Vfb net too. This doesnt make the
    LF noise go away.
    - I checked that the Vcc power (5V) to the switching controller is
    clean. This is a differnt Vcc from the noisy 5V regulator mentioned
    earlier.
    - Basic rules such as short fat planes for the noisy power portion,
    AGND isolated from DGND etc. are followed. I am not an expert though
    and may have violated some not-so-basic rule of layout.
    - If I look at the switching node on a scope I see that the duty cycle
    has a jitter of about 50 ns though the frequency is very constant. When
    all regulators (except the noisy G3 reg) is switched off, then the duty
    cycle jitter becomes much lower - about 10ns.


    Based on this my main conclusions (which may be incorrect) are:

    - The problem is not loop stability. When all regs except the noisy G3
    reg is switched off, the LF noise dissapears. Also the noisy G3 reg is
    isolated from the board which means that its load is not changing
    depending on whether the other regs are on or off. I havent done a load
    transient test yet though.

    - I am thinking there is somehow noise injected from a nearby regulator
    on the PWM ramp inside the controller chip because the LF noise is
    periodic and depends on whether a nearby controller of the nearly same
    freq is on or off. I am rationalizing the fact that changing the freq
    of the noisy reg wrt to the others means that their respective PWM
    ramps change their phase rapidly (convolve?) wrt to each other which
    makes the 'noisy' overlaps last for a shorter time.

    Is this a fair conclusion? If so how do I reduce this interference and
    how do I methodically find the source of this noise? What is the most
    likely entry point for such noise. I can re-lay out the board if
    necessary.

    I am sorry that I cannot publish the schematic and layout due to
    confidentiality issues.

    Thanks,
    QQ
     
  2. Joerg

    Joerg Guest

    Hello QQ,

    It is possible to see "motor boating" when a regulator becomes unstable.
    Duty cycles over 50% can cause RHP instability. However, if you have
    closely followed the data sheet, app notes and good layout practices
    this may be a lesser concern in your case, as you had said.

    What concerns me is that you mentioned split grounds. In such complex
    designs I have rarely seen that work. If I also count the EMC failures
    that clients with split ground design have experienced I could almost
    say that I have never seen it work. Try to connect the two planes
    tightly via short bridges every inch or so. These bridges should be less
    than 1/4" long or you'd have to use copper tape and solder. Then look at
    the noise again.
    That looks like the regulators are, to an extent, fighting with each
    other for load. A split ground can cause that and so can shared loads
    such as level translators. Problem is, in a partially digital design
    loads are not constant at all and that can cause modulation. Large RAM
    banks are often the dominant contributors and you can usually find their
    read/write patterns right on the supply nodes. If mounting large low-ESR
    caps on all the rails doesn't significantly help then the ground
    structure would become even more of a suspect.
    Do you have even more grounds than AGND and DGND? I'd try to tie the all
    together to see how the noise behaves then. "Thin nets" are in fact
    inductors.
    Again, controlled ground return paths in systems with several grounds
    are next to impossible unless you can guarantee that there will be no
    other paths than that single point return. However, this would mean that
    the system couldn't have any outside connections or each would have to
    loop through a substantial ferrite core.
    10nsec jitter is still pretty gross. Somehow that tells me there must be
    lots of cross contamination between circuits that aren't supposed to
    "see" each other.
    If this problem becomes stubborn and deadlines loom you might need the
    help of a consultant who knows about crosstalk, noise etc. It's not so
    bad, lots of companies use this kind of help in the same way that they
    use attorneys to vet their business deals. Even large ones do. But don't
    wait too long because worst case you may have to perform a re-layout.

    Regards, Joerg
     
  3. John Larkin

    John Larkin Guest


    Sounds like they're trying to phase-lock, or they're heterodyning, or
    something. Some switchers are sync'able to avoid this, but this one
    isn't. Try pushing the frequencies far apart; that might help.

    Moving them farther apart might help. Of if you can change the layout,
    just use syncable switchers and lock them all to some common clock
    available on the board. We just did a board with an LTC3407 dual
    syncable switcher (powering a big fpga, 1.8 and 3.3 volts) and locked
    it to the master clock on the board.

    John
     
  4. If you run eight, or even three, power oscillators close together, you
    should be more astonished that ALL of them don't show beat-note effects.
    Why one (two if you count the G5 one as well) shows the effect and not
    the others is probably due to the exact layout or maybe you have a
    slightly different circuit for the lowest voltage unit?

    I don't know how you solve the problem; SMPS are not my field. I suppose
    you can't run them all synchronized to a master clock?
     
  5. Mark

    Mark Guest

    I have seen this very problem, you are correct it is a beat note
    between two or more of the switching frequencies and it will vary with
    temperature and unit to unit becasue the switching frequencies are not
    well controlled. It may be very difficult to provide sufficent
    isolation to prevent this. A better approach would be to synchronize
    the switching frequencies.
     
  6. Pooh Bear

    Pooh Bear Guest

    Sounds like crosstalk to me. If you could sync all the PWM chips it might
    help.

    Ground noise is a possible source of the problem.


    Graham
     
  7. Terry Given

    Terry Given Guest

    In addition to the other pertinent comments, what about magnetic
    coupling between your chokes? if possible, use closed magnetic cores (eg
    toroids, pot cores or shielded drum cores). orienting adjacent magnetics
    at right angles to one another will also help. Many smps chokes have
    huge air gaps - ie use drum cores. Most of these are also available as
    shielded designs - a ferrite sleeve is placed around the assembly,
    spaced far enough away that it doesnt wreck the NIsat

    Cheers
    Terry
     
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