SMPS - effects of casing

[TP]

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current consumption.
I would be interested in the insights and experiences of others in
this area.

 

[PeteS]

You don't say whether this is your design or someone else's, or if the
metal case is grounded.

Whatever those things, the odds-on cause of your problem is poor layout
perhaps with poor design in the loop compensation network.

Switchmode supplies require great attention to layout (and indeed
should be modeled at the layout level if you have the tools) for both
stability and EMI issues.

If you designed the circuit, can you identify the key parameters (Vin
range, Vout, Iout range, Cin, Cout, controller?

Cheers
Pete

 

[TP]

They are my designs. I'm seeing similar problems in two very
different designs. Widely
different voltages and currents, different controllers and
frequencies, grounded and ungrounded cases. So what I am interested
in is general replies and perhaps specific anecdotes of similar
difficulties and solutions.

 

[Ken Smith]

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current consumption.
I would be interested in the insights and experiences of others in
this area.

If you use unshielded inductors and place a conductive case in the
inductors magnetice field, you can significantly change the inductance.

If you ground the PCB to the case in more than one place (a common
mistake) the case changes the ground wiring and can run the switching
spikes into the control circuit which can be bad news.

When you place it in the case, you often also change the cabling from the
test set up to the production one. If the loop stability is a bit flaky,
changing the impedance on the input wiring can make for loop oscillation.

When you put the converting into its case, it is running at a different
temperature. If you haven't made sure the circuit will work equally well
over the temperature range, this may be what you are seeing.

Last but not least, you may be wrong and the effect isn't happening at
all. The board in the case is a defective one or something that has lead
you down the garden path.

 

[Joerg]

Hello TP,

The are a few ways to approach this from an experimenter's side to narrow down the neuralgic points:

Hold a piece of the same kind of metal close to the circuit from different sides. About the same distance that the case walls would be. Any changes? For example, when coming close to the magnetics?

Next, do the same but now ground the metal to the PCB with a very short and wide braid. Hoping that there is only one ground, else you'd be in for trouble anyway.

Regards, Joerg

 

[John Popelish]

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current consumption.
I would be interested in the insights and experiences of others in
this area.

What kind of inductors are you using in these supplies? Some shapes
have almost no external field (toroids) and some have extended
external fields (drum cores).

 

[Genome]

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current consumption.
I would be interested in the insights and experiences of others in
this area.

That sort of behaviour seems strange.

I mean.

I might anticipate problems with EMI external to the design, and work to
exclude/minimize it, but I would be seriously dissapointed if it fucked its
own bucket after incorporation.

Perhaps it's because you are a top posting idiot?

DNA

 

[TP]

What kind of inductors are you using in these supplies? Some shapes
have almost no external field (toroids) and some have extended
external fields (drum cores).

Thanks to everyone who has reponded.

The inductors are toroids. There are common mode chokes on the input
and the output.

As the unit is slid into the case, the problem begins as the
controller IC enters the case. The problem can be seen on the scope
as irregular switching pulses--one to three maximum duty pulses
followed by one pulse too short to fully switch on the MOSFET.

The compensation loop has been suspected but does not appear to be the
culprit.

We have tried filtering the feedback input and the current sense
input.

The case is grounded at only one point.

The layout is crowded; case fit is tight.

This problem affects about 2% of the units produced. The problem can
be corrected by replacing the controller IC, but the IC manufacturer
has tested "bad" ICs and says they meet specification. The ICs of
some date codes have about 30% failure rate while others have no
failures. The IC manufacturer has sent an applications engineer to
see the problem firsthand. We have tried all of his suggestions to no
avail. It is a Linear Technology controller IC.

TP

 

[John Popelish]

Thanks to everyone who has reponded.

The inductors are toroids. There are common mode chokes on the input
and the output.

As the unit is slid into the case, the problem begins as the
controller IC enters the case. The problem can be seen on the scope
as irregular switching pulses--one to three maximum duty pulses
followed by one pulse too short to fully switch on the MOSFET.

The compensation loop has been suspected but does not appear to be the
culprit.

We have tried filtering the feedback input and the current sense
input.

The case is grounded at only one point.

The layout is crowded; case fit is tight.

This problem affects about 2% of the units produced. The problem can
be corrected by replacing the controller IC, but the IC manufacturer
has tested "bad" ICs and says they meet specification. The ICs of
some date codes have about 30% failure rate while others have no
failures. The IC manufacturer has sent an applications engineer to
see the problem firsthand. We have tried all of his suggestions to no
avail. It is a Linear Technology controller IC.

Sounds fascinating. Do you sell tickets for this show? ;-)
Is there any way to give us the particulars (schematic, photos of
layout, scope waveforms, etc.)?

Have you heard that the most interesting scientific discoveries are
not accompanied by the exclamation, "Eureka!" but by, "Now, that's
funny."

 

[legg]

Thanks to everyone who has reponded.

The inductors are toroids. There are common mode chokes on the input
and the output.

As the unit is slid into the case, the problem begins as the
controller IC enters the case. The problem can be seen on the scope
as irregular switching pulses--one to three maximum duty pulses
followed by one pulse too short to fully switch on the MOSFET.

The compensation loop has been suspected but does not appear to be the
culprit.

You are describing subharmonic oscillation, though. If the error
amplifier is generating the pattern, then it's not handling built-in
delays very well - it normally shouldn't be able to slew the control
signal from maximum to minimum in less than one switching cycle
interval, as this oscillation pattern would require.

We have tried filtering the feedback input and the current sense
input.

The short cycle cannot be noise-induced if power switch conduction has
not occurred to initiate the noise.

If there is some kind of slope compensartion generator present that is
dependant on the gate drive period, it is possible that you are
failing to discharge it properly at full duty cycle. This allows a
multi-stable chaotic condition for the controller.

Buffers or isolators with non-uniform slew rates - ie open collector
or emitter followers with oversized loads - can create the same
chaotic behaviour. This includes opto-couplers and shunt regulator
feedback elements.

The case is grounded at only one point.

Not such a great idea in an isolated converter, as both sides of the
isolation barrier need chassis returns for locally generated common
mode currents. The chassis ties selected should shorten the return
path to the specific noise sources.

The layout is crowded; case fit is tight.

Common mode chassis currents increase as capacity to frame of noisy
nodes increases. Returning these to a relatively noise-voltage-free
plane on the appropriate side of the isolation barrier prevents their
having to cross the isolation barrier from the side that owns the
shortest common-mode filter capacitors current path.

This problem affects about 2% of the units produced. The problem can
be corrected by replacing the controller IC, but the IC manufacturer
has tested "bad" ICs and says they meet specification. The ICs of
some date codes have about 30% failure rate while others have no
failures. The IC manufacturer has sent an applications engineer to
see the problem firsthand. We have tried all of his suggestions to no
avail. It is a Linear Technology controller IC.

Don't shoot the messenger by trying to blame the chip. It's trying to
tell you something. All you have to do is look closer. Test your
circuit above 75% duty cyle - the behaviour should show up in some
more modest form, without a full chassis - just a plate or partial
form that doesn't interfere with troubleshooting.

RL

 

[PeteS]

I agree with the unshielded parts, but I have seen the most unusual
effects with Linear Tech controllers (they are almost universally
current mode controllers).
Here's a very specific one to check:
Do any of the sense lines (Isense from the sense resistor if it has
one) or the voltage feedback path (almost always set for 0.8V at
nominal output) track in the area over the power ground area or over an
internal layer in the switching area?
I had to fix a circuit that had these issues - the effect was the
inductor (Cooper coilcraft) had to be put in in one direction to work
(the windings would affect the underlying circuitry because there was a
sense line via right underneath it).
The rule is to keep the sense lines short, clear of the high speed
switching and clear of the high current planes. Using a 4-wire layout
technique for the sense resistor is preferred, for instance.
The other thing is that the high current and switching zones should
have their own ground plane area (it *is* connected to the main ground,
but at a single point so eddy currents are mostly limited to a single
area). The currents in the ground and power plane (prior to the output
plane) can generate significant EMI and you have to treat them
accordingly.
So check the routing of your sense signals and whether the
power/switching plane(s) go beneath the pins of the control section of
the chip.
Cheers
PeteS

 

[John Popelish]

They are my designs. I'm seeing similar problems in two very
different designs. Widely
different voltages and currents, different controllers and
frequencies, grounded and ungrounded cases. So what I am interested
in is general replies and perhaps specific anecdotes of similar
difficulties and solutions.

Your problems sound like one of two things. either the closed loop
voltage control is poorly compensated (mistuned, in industrial control
parlance, or too much phase shift at unity gain) or the error
amplifier line is contaminated with noise from the switching process.
If I was working on this, I would look at the error amplifier output,
if it was available (connecting a scope probe directly to the error
amplifier input will probably change the situation too much) or the
switcher output if that is the closest I could get (though, it will be
harder to interpret). Then I would arrange to drive the input voltage
or the load with square pulse variations, so that I could watch the
control loop respond to those sharp, wide spectrum disturbances.

I suspect you would see either ringing, sub harmonic oscillations, or
chaotic reaction in the response. The case is just pushing a
continuous weakness over the edge. Once you can watch the control
response, you can see if particular experiments make things more or
less robust. The more robust examples (that damp the disturbances
faster and with less hunting) should better handle the variations
caused by the case.

 

[John Popelish]

TP wrote:
(snip)

This problem affects about 2% of the units produced. The problem can
be corrected by replacing the controller IC, but the IC manufacturer
has tested "bad" ICs and says they meet specification. The ICs of
some date codes have about 30% failure rate while others have no
failures. The IC manufacturer has sent an applications engineer to
see the problem firsthand. We have tried all of his suggestions to no
avail. It is a Linear Technology controller IC.

What Linear Technology part number? I would like to look at the data
sheet for clues to what might be causing your problems.

 

[TP]

TP wrote:
(snip)


What Linear Technology part number? I would like to look at the data
sheet for clues to what might be causing your problems.

Thank you John. The P/N is LTC 1871. SEPIC topology similar
to the example of page 29 of the data sheet except that there is
a MOSFET driver inserted in the gate drive line. Input is 10-35V,
tolerant to 100V. Output is 12V @ 4A. L1,L2 is a dual 22uH
toroid.

TP

 

[John Popelish]

Thank you John. The P/N is LTC 1871. SEPIC topology similar
to the example of page 29 of the data sheet except that there is
a MOSFET driver inserted in the gate drive line. Input is 10-35V,
tolerant to 100V. Output is 12V @ 4A. L1,L2 is a dual 22uH
toroid.

http://www.linear.com.cn/pdf/1871fas.pdf

Many questions come to mind, not the least of which is how you
tolerate 100 volts in, when the chip has an absolute input voltage
rating of 36, but never mind, for now.

The biggest problem with designing a reliable circuit with this chip
is the unspecified gm of the error amplifier (650 umho typ., no max.
or min.) So no matter how much gain the error amplifier has, from
zero to infinity, it meets data sheet specifications. But this gain
is an integral part of the design for stability. Can you post a
layout of your board that shows how the input and output filter caps
and source of M1 relate to the common pin on the chip and the feedback
divider connections? Trace inductance and resistance and capacitor
ESR can be major players in the noise that sees its way to the error
amplifier. The error amplifier input node (pin 3) is also quite
sensitive to capacitive pickup, if not shielded by the layout. It may
be helpful to parallel the resistive divider with a capacitive divider
to lower this node's impedance (divide capacitive coupling) at high
frequencies.

Another big variation in the gain and stability of the current control
is the resistance of the fet switch. The lower this is, the higher
the effective gain of the current control loop. In the extreme, if
the resistance of the switch approaches zero, the gain of the current
control loop approaches the open loop gain of the current sense
comparator. Yikes. That is a big drawback of using the fet
resistance as current shunt, instead of having an actual, known
resistance in the source lead as a shunt.

This chip gives me heartburn just looking at the data sheet. It is
optimistic enough to have been designed by a digital designer.

 

[legg]

Thank you John. The P/N is LTC 1871. SEPIC topology similar
to the example of page 29 of the data sheet except that there is
a MOSFET driver inserted in the gate drive line. Input is 10-35V,
tolerant to 100V. Output is 12V @ 4A. L1,L2 is a dual 22uH
toroid.

As the current sensor is on the drain of the fet, delays in turning
the fet on can abort a switching cycle, due to the late high voltage
signal still being present. You have introduced a driver in series
with the chips gate drive output, adding delays in the drive waveform
that are invisible to the IC.

How the chip normally handles this delay is not evident in the
functional schematic, so you can't tell how it's being defeated by
your mod.

One way would be to detect that drive output has exceeded the typical
enhancement thresholds expected - signalling full discharge of Cdg. If
you decouple the chip drive from Cdg using an external driver, this
feedback effect would be lost.

This is pure speculation. I haven't read the data sheet closely

RL

 

[Ken Smith]

Not such a great idea in an isolated converter, as both sides of the
isolation barrier need chassis returns for locally generated common
mode currents. The chassis ties selected should shorten the return
path to the specific noise sources.

If you hook both the input and output side to the chassis, the converter
is no longer isolated. Although this may help somewhat on the EMI,
grounding both sides of the input power helps more.

 

[legg]

If you hook both the input and output side to the chassis, the converter
is no longer isolated. Although this may help somewhat on the EMI,
grounding both sides of the input power helps more.

The connection, in both cases, is through coupling capacitors of
suitable voltage and safety class.

It appears that this is a non-isolated application, in any event.

RL

 

[legg]

As the current sensor is on the drain of the fet, delays in turning
the fet on can abort a switching cycle, due to the late high voltage
signal still being present. You have introduced a driver in series
with the chips gate drive output, adding delays in the drive waveform
that are invisible to the IC.

How the chip normally handles this delay is not evident in the
functional schematic, so you can't tell how it's being defeated by
your mod.

One way would be to detect that drive output has exceeded the typical
enhancement thresholds expected - signalling full discharge of Cdg. If
you decouple the chip drive from Cdg using an external driver, this
feedback effect would be lost.

Page 6 indicates that internal Leading-Edge-Blanking (LEB) is present.
There is no way of telling how the leading edge duration is set,
but using the drive rise-time would be the simplest method, and the
one who's accuracy is compromised by the use of a drive buffer.

Note that no published application circuit uses even the simplest
drive buffer, in spite of concerted warnings about chip overheating
due to fet gate loading. I would suggest that it's not an option.

Source resistor sensing IS an option noted in the apps which would
reduce the need for LEB.

According to the datasheet page3, the SENSE pin(10) current
switches from 5uA when gate drive is low, to ~40uA when the gate
drive is high. This theoretically allows an external hysterisis to be
introduced, by the introduction of a series resistor. There is no
application example of this current being used, in any way.

RL

 

[TP]

I agree with the unshielded parts, but I have seen the most unusual
effects with Linear Tech controllers (they are almost universally
current mode controllers).
Here's a very specific one to check:
Do any of the sense lines (Isense from the sense resistor if it has
one) or the voltage feedback path (almost always set for 0.8V at
nominal output) track in the area over the power ground area or over an
internal layer in the switching area?
I had to fix a circuit that had these issues - the effect was the
inductor (Cooper coilcraft) had to be put in in one direction to work
(the windings would affect the underlying circuitry because there was a
sense line via right underneath it).
The rule is to keep the sense lines short, clear of the high speed
switching and clear of the high current planes. Using a 4-wire layout
technique for the sense resistor is preferred, for instance.
The other thing is that the high current and switching zones should
have their own ground plane area (it *is* connected to the main ground,
but at a single point so eddy currents are mostly limited to a single
area). The currents in the ground and power plane (prior to the output
plane) can generate significant EMI and you have to treat them
accordingly.
So check the routing of your sense signals and whether the
power/switching plane(s) go beneath the pins of the control section of
the chip.
Cheers
PeteS

Thanks, Pete.

It is a 2-layer board. There is a small ground "island" under the
controller circuit with a short trace back to a central gounding
point. This island does not have high power going through it.
I found earlier that rotating the mounting position of the sense
resistor by 90° did appear to correct the problem at that time.
However, the problem has reoccured since.

TP