slope compensation

Discussion in 'Electronic Design' started by Heindorf, Jan 18, 2005.

1. HeindorfGuest

Hi all,
somehow I can't get the point of slope compensation.We're currently
working on a power supply, full bridge phase shifted voltage mode with
the LTC3722-2.Now there is an imbalance in the current distribution of
the 2 legs.To tackle the problem current mode control is recommended.The
IC supports both modes.It is also shown that to avoid instability a
slope compensation should be added for duty cycles>50%.Does that mean
that my available output current decreases also to 50%?
Let's take our example. At full power we get at 99% duty cycle approx.
10A Bridge current corresponding to 4.5V Error Amplifier output.If I
insert now a 0.45 Ohm resistor I get 4.5V at 10A.If I add a slope
compensation would I decrease the duty cycle and hence the bridge
current? Or do I need another transformer to get the same power with 50%
duty cycle? I have here some conceptual difficulties I guess.
Rolf

2. Mook JohnsonGuest

search the TI website under power management. There are plenty of
explanations in the application notes on exactly what slope compensation is
and how to implement it.

3. HeindorfGuest

Hi Mook,
I've already read some app. notes in this respect and wouldn't have posted if
there were
not so many important questions unanswered, at least for me.
Rolf

4. Ken SmithGuest

Without slope compensation, the current fully controls the pulse width.
When you add slope compensation, you are effectively lowering the gain of
the local feed back loop by reducing the amount of control the current has
on the pulse width.

In continuous mode, the pulse width this cycle has an effect on the
current in the next. This means that there is a phase lag. If you allow
the gain to be unity or more when this phase lag reaches 180 degrees, this
local loop will want to oscillate. It is near imposible to make the
overall loop have enough gain at these frequencies to prevent this
oscillation. As a result, you need to lower the gain of the local loop.

In a bucker, the exact same circuit can serve a different purpose. If
there is an upwards step on the input voltage of a discontinuous bucker,
the output of a current mode bucker will dip. This is because less charge
gets through the inductor before the transistor is turned off. In a
non-current controlled circuit, the output would rise. You can balance
one against the other to make one that is less sensitive to the input
voltage changes.

5. Guest

I'm not sure from your description if the symptom you're experiencing
is 'flux walking', but it may be. It is very difficult to avoid having
to AC couple full-bridge converters, even with current mode control.
Flux walking is the tendency toward a DC bias developing due to any
imbalances in the primary waveform. Current feedback control
theoretically prevents this, but, in practice, it fails to prevent it
under any circumstances in which feedback gain is insufficient. I
suggest that you investigate this possibility.
Slope compensation is normally used to counteract the feedback control
instability associated with duty factors near and above 50%. The high
DF means that the system might have insufficient off-time to respond to
input perturbations linearly, resulting in a Right Half Plane zero in
the control loop transfer function. One way to implement slope
compensation is to lower primary inductance, thereby increasing
magnetizing current, which adds to slope compensation, since primary
current feedback includes magnetizing current. Study this topic
carefully. Many designers don't really understand what they're doing
in this area.
Paul Mathews

6. leggGuest

Slope compensation amplitude is applied relative to the slope normally
present in the sensed current, which is the di/dt of the main
filter/storage inductor. Normally the inductor current ramp is
expected to be only a small portion of the peak or average current
being sensed. Added slope greater than 1/2 the natural ramp is
overkill.

If you are using your controller's absolute peak current limit as a
limiter for output current, then any superimposed signal will reduce
the output current by that factor, unless it is taken into account.

As this limit is seldom intended as an accurate feature, it is
normally set considerably higher than the intended rated output of the
circuit, in any event. Close tolerance current limiting requires
additional circuitry, and is generally unneccessary in a fault
protection feature.

RL

7. GenomeGuest

Hope you're on a fixed width font....

"Hi all, somehow I can't get the point of slope compensation."

Me neither......but, if you are using 'peak' current mode control then your

__________________________________________ error signal
/| /| /| /| /| /|
| | / | | | / | | | / |
| | / | | | / | | | / |
| |___| |__| |____| |__| |____| |__ primary current sense signal

|_____|______|______|______|______|______| clock signal

/| /| /| /| /|
/ | / | / | / | / |
/ | / | / | / | / | /
/ | / | / | / | / | /
/ | / | / | / | / | /
/ |/ |/ |/ |/ |/ ramp signal

When you were expecting this...

__________________________________________ error signal
/| /| /| /| /| /|
/ | / | / | / | / | / |
| | | | | | | | | | | |
| |__| |___| |___| |___| |___| |__ primary current sense signal

|_____|______|______|______|______|______| clock signal

/| /| /| /| /|
/ | / | / | / | / |
/ | / | / | / | / | /
/ | / | / | / | / | /
/ | / | / | / | / | /
/ |/ |/ |/ |/ |/ ramp signal

With peak current limiting the answers are the same.

Unfortunately your supply is guaranteed to lock itself
into the first one, AKA subharmonic oscillation.

I can't explain why it should, I'm thick as a brick.

part of the ramp signal to the current sense signal.

Something late has more ramp and gets terminated earlier.
Something early has less ramp and gets terminated later.

So they sort of get equalised.

The magic sum is... can't remember... but if you add half
the equivalent sensed inductor downslope then your supply
will be dealing with average output current.

Which might be quite good.

The other magic sum is you can do something else that makes
your supply invarient to the input volts or somesuch.

current limit depends on the peak sensed current.

That means you get to solve the 'Three Resistors From Hell'
problem and worry about what happens when the supply goes
into current limit.

DNA

8. HeindorfGuest

Hello Genome,
thank you for your efforts and also all the other answers.We have a fixed
frequency configuration.I must think about all ideas and remarks-quite a lot of
stuff so far.But one main concern of me hasn't been addressed, I suppose.In a
bridge topology with a power transformer I design the transformer for 100% DF
(voltage mode).If I now slope compensate the circuit to below 50% in current
mode, do I need another transformer or is this compensation never applied to
(phase shifted) bridge configurations?
There is a lot unclear to me.
Rolf

9. leggGuest

The simple addition of slope compensation would not affect your
controller's duty cycle limits.

This limit is unlikely to be 100%, using most of the available control
devices, particularly at full load. This is due to arbitrary
imposition of a minimum dead-time, and the inability of power switches
to reverse large currents in the primary, without delays.

RL

10. HeindorfGuest

Hi,
please don't take the 100% so seriously.What I don't understand is your other
statement.I add slope compensation, get a DF below 50% and don't affect the duty

11. Guest

1. In full-bridge converters operating in Continuous Current Mode (CCM,
where the smoothing inductor current never goes to zero) with
approximately constant DC voltage input, average power output and
average DF are not linearly related. The instantaneous value of Duty
Factor varies to maintain regulation, but the average value of DF
depends mainly on input to output voltage ratio and turns ratio. As
the load draws more power from the secondary, the DC current in the
inductor rises along with load current. Of course, the ripple current
in the inductor (which is the primary ripple reflected through the
turns ratio) increases in amplitude as load current rises, but this
ripple is typically only about 10% to 30% of the DC current. In other
words, double the load doesn't require double the DF. (To put it yet
another way, the transformer in a full-bridge converter acts like a
power transformer.)

2. Full-bridge converters drive the primary with alternating polarity
pulses. In order to prevent core saturation, these pulses must have a
net volt-seconds integral (sum) of zero. If this doesn't obtain, even
if imbalances are small, the core will eventually saturate (flux
walking). Many methods have been developed to prevent this, most
notably: air gaps in the core and capacitive coupling of the primary.
In theory, current mode feedback control also prevents the flux walking
phenomenon. In practice, it is difficult to achieve balance using
feedback over the great variety of operating conditions, including

3. Using peak current for feedback has its advantages, but one
disadvantage is the susceptibility of the system to subharmonic
oscillations. Much good literature is available on this subject. I
suggest starting at:

http://www.ridleyengineering.com

The TI/Unitrode Switchmode seminar series is also easy to find on the
web and full of great information. Here's a paper you should memorize:

http://www.powerdesigners.com/InfoWeb/design_center/Appnotes_Archive/u111.pdf

4. If there is any tendence toward subharmonic oscillation in a
full-bridge system, then you are almost guaranteed to have flux walking
problems. This is because all the even subharmonics have DC offsets.
For example, the first subharmonic has different amplitudes for every
other controller cycle. For a full-bridge, this means that the
positive half-cycles are offset from the negative half-cycles. Yikes!
For this reason, until I have a stable control loop, I ALWAYS
capacitively couple the primary of any full-bridge converter. IFF I'm
able to achieve the phase margins that I need, I SOMETIMES return to DC
coupling.

Paul Mathews

12. leggGuest

The addition of slope compensation will not affect the duty cycle (~
Duty Factor), nor will it affect the duty cycle limit of the
controller.

Your reference to 50% duty may be confusion over the noted fact that,
for some of the affected topologies, stability is achievable without
compensation, below 50% duty. This is the only reason a writer would
mention slope compensation and 50% duty cycle on the same page.

Duty cycle is primarily determined by input/output voltage ratios,
(reflected through the isolating transformer turns ratio, as may be
the case).

RL

13. Ken SmithGuest

Also, Linear makes PWM chips that raise the current limit automatically to
back out the current limit reduction.

It is also posible to do something like this:
Vref
!
/
\
/ R1
\
D1 !
Gate ----S<---+
drive ! Buffer1 C2 Buffer2
+--!>---------!!--+--+--!>---------- To slope comp
! ! !
--- \ !
---C1 R2/ --- D2
! \ ^
GND ! !
Vlimit

Both buffers are running on Vcc and ground so they can't follow signals
that go below ground. R1 and C1 make a ramp of a few volts. R2 and C2
have a TC that is much longer than a cycle of the converter. D2 limits the
positive swing of the ramp to about the same voltage regardless of the
duty cycle. A circuit like this backs out the effect of the slope
compensation over modest amounts of time. There are some transient
response issues to watch out for because for a sudden load change,
the slope-compensation is not right until C2 settles at the new voltage.

14. HeindorfGuest

Hello all,
thanks for all contributions. I think it will help me a lot.
Regards
Rolf