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Single Supply System

Discussion in 'Electronic Design' started by Richard Bair, Jan 28, 2004.

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  1. Richard Bair

    Richard Bair Guest

    What is a good way to separate DVDD and AVDD in a singly supply system? I
    want to isolate the AVDD power for an ADC from and digital noise. I
    already have separate ground planes on the same layer (two layer design)
    but still wish to tweak my 24-bit ADC performance a bit.

    This is what I currently have:

    DVDD ----/\/\/\/\/\--------------------------AVDD
    | 120 Ohm |
    | |
    |
    5V Reg ----- 10 uF
    | -----
    | |
    | |
    DGND AGND

    Does this configuration seem ok? What about the values? Also, are certain
    capacitor types better in this situation?

    Thanks,
    Rich
     
  2. How much current is being drawn from AVdd? Is that a ceramic cap? If
    voltage drop is a problem, an SMT ferrite bead can help. Watch DC
    problems as well as the AC stuff.

    Best regards,
    Spehro Pefhany
     
  3. Richard Bair

    Richard Bair Guest

    AVDD current should be ~240uA. Currently the cap is ceramic. AVDD powers
    the ADC and an internal Vref within a MSC1210Y5 microcontroller. To
    clarify, there is also a cap in parallel with the previous drawing of 0.1
    uF to AGND directly off the AVDD pin. What I am trying to remove is some
    spread in Vpp in Vref when I AC couple with an oscilloscope and have
    certain digital features of the PCB enabled. For example, when I enable
    the IRDA interface there is an extra clock line of 11.0592MHz. Or when I
    leave RS485 communications connected I notice some noise from the port
    powered converter that comes in on the A and B lines. I am attempting to
    read two platinum RTDs ratiometrically using a simple voltage divider
    circuit and a polynomial fit. I think I've done my due diligence on the
    separation of digital and analog ground planes on the same layer...they
    connect directly under the microcontroller. The circuit and polynomial fit
    is such that the average voltage step between 1/10 Celsius is ~39 uV over
    the temperature range of -200 to 60 Celsius. I average (in hardware) 16
    ADC conversions for each channel an want my display to be stable to +/- 0.1
    C...I get this with the two aforementioned options above deactivated. My
    stability test data using a decade box is more like +/- 0.3 C with the
    aforementionee features activated. Consecutive display/conversion cycles
    only change by 1/10 but long term I see the increased window.

    Thanks,
    Rich
     
  4. You might want to talk to the TI people (in Tucson) to see if they can
    give you some hints. I talked to them in general terms about just this
    kind of issue on this product a couple of months ago and they seemed
    relatively knowledgable. Just took a quick look, and I don't see the
    business cards 8-(. I would maximize the capacitance from Avdd to
    Agnd, and try to maximize the PGA gain, of course. It might be a good
    idea to parallel the resistor with Schottky diodes back-to-back, but
    that's another issue.

    What do you mean by "ratiometric" in this context? Do you have the two
    RTDs and a single precision resistor all in series? Or two resistors?

    Best regards,
    Spehro Pefhany
     
  5. Richard Bair

    Richard Bair Guest

    Thanks. I have Vref going through a precision resistor then through the RTD
    resistance to AGND. I have two of these "circuits," one for each RTD. The
    ADC inputs are between the resistors. I meant that the RTD circuits were
    referenced to the same supply and ground as the ADC.

    On another note, I wired in a 78L05 100mA 5V regulator today. Nothing like
    surface mount bench top work 8>) I took the 12 VDC input referenced the
    '05 part to AGND and took the output to a 47 uF in parallel with a 0.1 uF
    directly off the AVDD pin. Vref looked a little cleaner but over night
    tests should tell. Do you thik an external reference would be better? I
    was trying to avoid the cost of one. Also, with the '05, I should
    reference the analog supply to AGND not DGND, right?

    Also, it sounds like you have some experience with this part. If I lower
    the precision resistors I effectively increase the voltage step betwen 1/10
    C steps at the cost of loading Vref. The spec shows that 100 uA with 3
    Ohms output impedance. The Vref load graph looks like it can load out to
    500 uA without too much hastle...I've tested at ~200 uA and the reference
    doesn't look degraded...any thoughts? I don't have a good understanding of
    what will happen to the output impedance of Vref if I load Vref further and
    what risks are introduced. I am using PGA = 1 and 0-2.5 Volts maps to 0 to
    0xFFFFFF counts. Will I see much of a benefit by raising this even if 1
    bit is only worth ~0.149 uV? I guess it would shift the readings away from
    ground and the noise floor. Currently, the inputs could range from ~18-117
    mV over -200-+60 Celsius. I also have the ADC buffer on which should
    maximize its' output impedance which I suppose makes the reading more
    accurate by not source additional current during the conversion...is that
    the right understanding? Would I gain anything by lowering the reference
    to 1.25 V in terms of stability? The ADC would then be at 0.075nV per bit;
    however, this would begin to minimize the voltage step between 1/10
    Celsius...that said, I could lower the precision resistors too since the
    Vref load would be less at 1.25V.

    Thanks for the help,
    Rich
     
  6. N. Thornton

    N. Thornton Guest

    Hi Rich.

    One thing I'm not hearing yet is measurements of how much each
    significant Vpoint can change, and how much effect each change has on
    the final accuracy. That can locate your error sources so you know
    what to tackle. And what not to tackle.

    I dont know what youre doing exactly with AVDD, ie the circuit details
    from that to your Vref, nor do I know the circuit details upto the
    filter above. But I notice your filter time constant is small and will
    not remove small changes in V level caused by the varying loading on
    DVDD. A digital power line running devices with at 11MHz clock will
    normally have some low f components as well. So far I havent seen how
    youre dealing with that.


    Regards, NT
     
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