N
Nico Coesel
- Jan 1, 1970
- 0
Some food fo thought:
I'm working on a new design in which I need to bring 64 LVDS (250Mbps
each/ 125MHz fmax) lines into a Spartan3 FPGA. The distance between
the source and the FPGA is less than 2" / 5cm. Ofcourse there is a
solid ground plane underneath the signals (the board will have at
least 4 layers).
I'm wondering if I can save a lot of pins if I feed the LVDS signals
single ended into the FPGA (terminate the pair close to the FPGA and
leave one end dangling). I could bias the Vref pins on the FPGA to the
centre point of the LVDS signal. If I set the input pin type to GTL it
should work on paper. The LVDS signal has enough swing to exceed the
minimum signal amplitude.
Anyone ever tried this?
I'm working on a new design in which I need to bring 64 LVDS (250Mbps
each/ 125MHz fmax) lines into a Spartan3 FPGA. The distance between
the source and the FPGA is less than 2" / 5cm. Ofcourse there is a
solid ground plane underneath the signals (the board will have at
least 4 layers).
I'm wondering if I can save a lot of pins if I feed the LVDS signals
single ended into the FPGA (terminate the pair close to the FPGA and
leave one end dangling). I could bias the Vref pins on the FPGA to the
centre point of the LVDS signal. If I set the input pin type to GTL it
should work on paper. The LVDS signal has enough swing to exceed the
minimum signal amplitude.
Anyone ever tried this?