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Single ended LVDS into FPGA

Discussion in 'Electronic Design' started by Nico Coesel, Aug 1, 2009.

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  1. Nico Coesel

    Nico Coesel Guest

    Some food fo thought:

    I'm working on a new design in which I need to bring 64 LVDS (250Mbps
    each/ 125MHz fmax) lines into a Spartan3 FPGA. The distance between
    the source and the FPGA is less than 2" / 5cm. Ofcourse there is a
    solid ground plane underneath the signals (the board will have at
    least 4 layers).

    I'm wondering if I can save a lot of pins if I feed the LVDS signals
    single ended into the FPGA (terminate the pair close to the FPGA and
    leave one end dangling). I could bias the Vref pins on the FPGA to the
    centre point of the LVDS signal. If I set the input pin type to GTL it
    should work on paper. The LVDS signal has enough swing to exceed the
    minimum signal amplitude.

    Anyone ever tried this?
     
  2. Nico Coesel

    Nico Coesel Guest

    The datasheet of the source chip specifies that. I more or less assume
    the source chip has the same centerpoint on all outputs.
    IMHO you don't need a signal that is always toggling. If you connect a
    resistor to each leg of the pair and a capacitor to ground (resistor
    divider between the two legs) then the voltage across the capacitor
    should be the centre voltage no matter what the LVDS signal looks
    like.
     
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