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Simple pulse generator circuit

Discussion in 'Electronic Design' started by iCod, Sep 25, 2012.

  1. iCod

    iCod Guest

    I need to generate a clean pulse variable from10nS to 250nS twice
    a second 2Hz. I'm sure there is a chip out there that will do this?
    I have tried a 555 for the 'long' time but the rising edge is too
    dirty to derive a clean narrow pulse. Any ideas or pointers greatly
    appreciated.
     
  2. Neon John

    Neon John Guest

    Bring your incoming signal into one terminal of an XOR gate. Pass the
    same signal through a buffer or two inverters in series to the other
    input of the XOR.

    When the incoming signal goes high, so does the output of the XOR -
    until the incoming signal propagates through the buffer(s), whereupon
    the XOR output goes low again.

    Choose your logic family and the number of buffers to set the width
    ouf your output pulse.

    IF you pass your incoming signal through a Schmitt trigger first, you
    can clean up the 555 output and use it to generate the twice per
    second trigger pulse.

    John
    John DeArmond
    http://www.neon-john.com
    http://www.fluxeon.com
    Tellico Plains, Occupied TN
    See website for email address
     
  3. Sounds like a job for a one shot.
    74HC123? But maybe something else is faster?

    George H.
     
  4. I did quick search on digikey and it looks like the AHCT sereis is
    faster. (to meet the 10ns spec.)

    I should order some, Say is there a good site that discusses the
    differences between the various logic families? HC, HCT, AHCT.

    George H.
     
  5. hamilton

    hamilton Guest

    How did you get a 555 to pulse at 10 Nano-Sec ??!!

    10 nS is 10 Mhz !

    Ok, do you require 10 -> 250 nS in one nS steps ?

    That would require a CPLD or FPGA to do that.

    A CPLD with a 200 Mhz clock would be able to give you a 1nS step.


    You can still use the 555 for the 2Hz part. ;-)
     
  6. hamilton

    hamilton Guest

    Boy, I must not be awake yet.

    10 nS is 100 Mhz !!!

    So two clock edges of 200 Mhz = 10 nS

    Two clock edges of 2,000 Mhz = 1 nS !!!

    Are you sure you want 1 nS resolution ?

    If so, you will need some FAST FPGAs !!
     
  7. Yeah... maybe a faster process.
    The AHCT series?

    http://www.ti.com/lit/ds/symlink/sn74ahct123a.pdf,

    lists a minumum tsubw of 5ns. That sounds promising.

    But the graphs don't look so good.

    George H.
     
  8. Yeah, Sorry I made a mistake and was reading the wrong parameter.

    I seem to remember getting 50 ns from a 74LS123 (or 221)

    The double pulser with one swallowing most of the other is a nice
    trick.
    (I'd just forgotten about it.)

    George H.
     
  9. mike

    mike Guest

    And what are you using to measure the result to see how it conforms
    to all of the above?

    This smells like one of those projects that starts out with a vague
    concept that gets tweaked into a nightmare scenario.

    Last time I saw anything with a billion-to-one ratio, it ended up
    as a digitally gated master clock in a multi-section cavity to keep one
    end of the board from talking to the other.
     
  10. hamilton

    hamilton Guest

    The OP has not define the resolution !

    10 - 250 ns in 1 ns steps or
    10 - 250 ns in 10 ns steps or
    10 - 250 ns in xx ns steps ???


    Also, did the OP state how the control would be handled.

    A carbon pot on a (xxx) analog timer chip would be all over the map
    and add offsets over temp.

    What a mess !

    If the OP is still around, what do you have in mind here ??

    hamilton
     
  11. Are there any better ones?
    I've got some 74LS221's left over from an old insturment. (not very
    fast)

    I really would like a fast double pulser, with variable delay.

    George H.
     
  12. Thanks I'll give it a 'look see'. I don't really care about stable.
    (I want to simulate PMT pulses.)

    George H.
     
  13. miso

    miso Guest

    Dammit, stop making sense!
    I'm with Jim on this one.

    One shots in general are a bad idea. I went through great pains on a
    multi-person design to use a counter to get around the one shot, only to
    find in a power down mode the crystal was turned off. Fortunately, other
    mistakes were in the chip so it wasn't like my screw up solely was to
    blame for blowing up the design budget.

    The trouble with one shots is they can be influenced by power supply
    noise, temperature to some extend if gate delays are part of the
    equation, etc. By the time you design a one shot as good as a Swiss
    watch, it ends up being an analog beast.
     
  14. Robert Baer

    Robert Baer Guest

    Use the 555 to drive a one-transistor one-shot..
     
  15. Bill Sloman

    Bill Sloman Guest

    An ON-Semiconductor MC100EP195

    http://www.onsemi.com/pub_link/Collateral/MC10EP195-D.PDF

    offers a digitally programmable delay from 2nsec to 12nsec. You can
    run the same pulse through one or - maybe easier - two of these parts
    under the control of a programmable counter until you've built up the
    20 to 250nsec of delay the OP is asking for, and then release the
    timing pulse after that delay.

    More complex than a monostable, and the propagation delay through the
    MC100EP195 is depressingly temperature dependent - the maximum delay
    increases by 6% from 25C to 85C and is decreased in the same
    proportion at -40C, and the minimum delay changes about twice as fast,
    but it might be good enough for use in an air-conditioned lab.

    On the other hand, it's ECL so the power rails will be clean and the
    edge transitions quick - about 100psec. You've got to route your logic
    along traces that look like terminated transmission, but at least ECL
    is designed to drive terminated connections.

    It would make an odd mix with a 555, but this may be one of those rare
    occasions where a 555 is the easiest quick and dirty option - albeit
    it very dirty.
     
  16. Guest

    a cpld, 10 lines of verilog and a 100MHz oscillator, something like
    xc9536xl for example

    26bit counter to give you ~2Hz, 5 bit counter to give you 10 to 310ns
    pulse in 10ns steps

    if you want pulse lengths that are not a multiple of 10ns, use a
    different oscillator

    -Lasse
     
  17. Bill Sloman

    Bill Sloman Guest

    And a 221 beats a dual 123 in any application where you don't need to
    retrigger the monostable. As Jim Thompson pointed out, the 123 is
    crummy monstable. He didn't bother to point out that 121 is a whole
    lot better if you don't need to retrigger.

    The advantage of the ECL part lies in the quality of the pulse edges
    it generates, and the stab\ility of the delay, particularly against
    power rail noise. The 121 and 123 are essentially analog comparators
    looking at a relatively slow ramp. Any noise on the ramp or the
    voltage the comparator is using as a reference create a lot more
    jitter than the same power rail noise would create in the ECL system,
    and the power rails in an ECL system are pretty much guaranteed
    quieter than the power rails in a TTL system.

    And the ECL system does lend itself to self-calibration schemes, where
    you calibrate the delay generating engine from time to time by getting
    it to produce a pulse-width modulated waveform, where the repeat time
    is controlled by a much more stable clock - which could be derived
    from an off-air standard, traceable back to something at the local
    National Bureau Standards.

    Here you could go for a 3MHz repeat cycle and use the delay engine to
    vary the high time from say 35nsec to 285nsec. Digitise the filtered
    DC content of the waveform and you've calibrated the delay engine
    against the 3MHz clock.

    In practice you'd derive the 3MHz clock from a good 10MHz clock and
    generate two additional 135nsec and 235nsec "high" period waveforms by
    adding in one or two periods of the 10MHz clock, allowing you to
    interpolate between exactly known PWM waveforms and the waveforms
    being calibrated.

    You can find and calculate out more subtle errors by repeating the
    procedure with slower clocks - say 2.5MHz and 2MHz.
    It would be a whole lot better way - if more expensive and complicated
    - if you designed it right.
    Perhaps. Does it do any self-calibration? TTL is a a bit of a problem
    if you are serious about getting accurate low-jitter timing signals.
     
  18. Bill Sloman

    Bill Sloman Guest

    Pity about that. ON-Semiconductor don't make them any more, and don't
    seem to have any ECLinPS equivalent

    http://www.onsemi.com/PowerSolutions/product.do?id=MC10198FN
    I used them in the 1980's in the beam blanker for Cambridge
    Instruments voltage contrast electron microscope.

    In fact I used several. One generated pulses wider than about 100nsec,
    range-switched by switching in a variety of timing capacitors, the
    other generated pulse in the 20nsec to 100nsec region, controller by
    adjusting the ramp generating current. For the narrowest pulses 5nsec,
    2nsec, 1nsec and 0.5nsec we split a 10nsec ecl pulse and fed one copy
    - as a "start" pulse into into one side of a NOR-gate built with
    discrete broad-band transistors while the other copy, after routing
    through a series of small delays realised as loops of miniature coax,
    hit the other side of the gate as a "stop" pulse.

    Very nice parts. It's a pity that they've gone obsolete.
     
  19. Bill Sloman

    Bill Sloman Guest

    10K ecl is a bit dated now. Back in 1995 I published a comment in
    Rev.Sci, Instrum,

    http://ieeexplore.ieee.org/xpl/logi...re.ieee.org/xpls/abs_all.jsp?arnumber=4993539

    Amongst other things I objected to the offending authors making a fuss
    about 10k being four times faster than TTL, when ECLinPS - which had
    been freely available for a year or two by then - was four times
    faster than 10K.
    The 74221 has a typical minimum pulse width of 47nsec with a no
    external timing capacitance. Worst case limits are 20nsec and 70nsec.

    This is incompatible with the 10nsec to 250nsec pulse width requested
    by the OP. There are lots of ways that you could shave the pulse down
    a bit to reduce that worst case 70nsec down to 10nsec, but none that
    would be all that trustworthy, and it's certainly not the single chip
    solution that the OP asked for.

    As Jon Elson pointed out the MC10198 would have done the job
    beautifully, but ON-semiconductor don't make it any more.

    The MC100EP195 isn't a single chip solution, and wrapping it up in
    enough supporting logic to do the job wouldn't be trivial, but it can
    be guaranteed to work, and work very well, if the job is done
    carefully. You'd want to do it on a four layer board, and make all the
    connections 75R micro-strip. The pulse width would then programmable
    in 10psec steps and the pulse edges would be very clean.

    The temperature dependence of the delays is a pain, but it looks as if
    it would be smooth and predictable. One might be tempted to glue a
    Peltier junction onto the top of the MC100EP195, and big heatsink on
    top of that, and regulate the substrate temperature to a millidegree
    or two, if one could work out how to sense the temperature inside the
    MC100EP195 package, by perhaps exploiting one of the protection diodes
    as a thermometer.

    Buying in a pulse generator is a much better idea, but no fun.

    <snip>
     
  20. Jamie

    Jamie Guest

    Use C555 which has a 15ns raise/fall to drive this.
    R3 sets the pulse width..

    Jamie

    Version 4
    SHEET 1 880 680
    WIRE -48 112 -64 112
    WIRE 192 112 192 96
    WIRE 192 112 160 112
    WIRE 192 128 192 112
    WIRE -64 144 -64 112
    WIRE 32 144 32 112
    WIRE 160 144 32 144
    WIRE 32 160 32 144
    WIRE 368 160 224 160
    WIRE 80 176 80 112
    WIRE 112 176 80 176
    WIRE 160 176 112 176
    WIRE 192 224 192 192
    WIRE -64 240 -64 224
    WIRE 32 256 32 240
    FLAG 192 224 0
    FLAG 192 16 0
    FLAG 112 256 0
    FLAG -64 240 0
    FLAG 32 256 0
    SYMBOL Comparators\\LT1720 192 96 R0
    SYMATTR InstName U1
    SYMBOL voltage 192 112 R180
    WINDOW 0 24 96 Left 2
    WINDOW 3 24 16 Left 2
    WINDOW 123 0 0 Left 2
    WINDOW 39 0 0 Left 2
    SYMATTR InstName V1
    SYMATTR Value 5
    SYMBOL res 96 160 R0
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL res 176 96 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL Misc\\signal -64 128 R0
    WINDOW 3 -24 154 Left 2
    WINDOW 123 0 0 Left 2
    WINDOW 39 0 0 Left 2
    SYMATTR InstName V2
    SYMATTR Value PULSE(0 5 .5u 15ns 15s .25 .5)
    SYMBOL res 48 96 R90
    WINDOW 0 -8 19 VBottom 2
    WINDOW 3 -60 52 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 5k
    SYMBOL ind 16 144 R0
    SYMATTR InstName L1
    SYMATTR Value 500µ
    TEXT -88 8 Left 2 !.tran 1us
    TEXT -144 88 Left 1 ;C555 2Hz signal
     
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