Connect with us

Simple Combinational System Design

Discussion in 'Electronics Homework Help' started by vick5821, Oct 20, 2012.

  1. vick5821

    vick5821

    700
    0
    Jan 22, 2012
    Hey there

    [​IMG]

    For this circuit design, how can I implement it ? What IC can I used in the implementation of the system ?

    Thank you :)
     
  2. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    step 1:
    find a suitable binary representation of the decimal number. For example youi could use straigt binary numbers, or you could choose BCD (binary coded decimal) or 1-ou-of-n code. You need to know how the decimal number is represented in order to devise a decoder.

    step 2:
    write down how the letters of the alphabet are displayed on the 7-segment display. Obviously you have 7 lines, one for each segment. Which lines are active for each letter?

    step 3:
    devise the logic for the decoder from the decimal number to the 7-segment wires using standard logic design methodologies, e.g. karnaugh maps. You can use standard logic gates like NAND, NOR; Inverter etc. for this.

    step 4:
    implement. Watch out for the type of 7-segment display you are using: common anode or common cathode. And don't forget the current limiting resistors for each LED in the 7-segment display.


    Alternatively you could use the decimal number as the address to an 8-bit wide EPROM and program the EPROM to give the corresponding code for driving the display. That, however, is most probably not was your instructor meant when he assigned this task.
     
  3. vick5821

    vick5821

    700
    0
    Jan 22, 2012
    I think I have to use a 7 segment decoder IC is it ?
     
  4. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    That will not work. A 7-segment decoder IC has built-in logic for displaying numbers, not letters of the alphabet.
    You will have to devise your own logic.
     
  5. vick5821

    vick5821

    700
    0
    Jan 22, 2012
    Hey, so this is what I constructed based on the given table. Is this correct ? What's next ? Karnaugh Map ?

    [​IMG]
     
  6. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    Looks o.k. at a quick glance.
    Next step is the synthesis of the logic. Karnaugh maps re one good tool.
     
  7. CocaCola

    CocaCola

    3,635
    4
    Apr 7, 2012
    This description is awkward for me to describe so hopefully you can follow...

    One thing I will note, it might be easier to map to the 0 logic state change vs the 1 logic as the zero logic only contains a max of 3 state changes at any given time...

    Basically want I'm saying is assume the 7 segment is always 1111111 and change the 0s (max three changes) to derive at the final value, instead of starting at 0000000 that can require up to 7 changes of state to display the final value...
     
  8. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    25,174
    2,690
    Jan 21, 2010
    In addition to that, it may be easier to perform the analysis for each segment.

    Start with the f segment. The logic for that is trivial.

    Searching for dependencies between segments first will reduce the amount of work you need to do. Are any always on or off when another one is on or off? Is the logic required to handle this dependency easier than determining its state from the 4 input bits?

    Personally, I'd rearrange your list so that it was in order of the binary input. That may also highlight some patterns.

    edit: I would also investigate grouping the segments in various orders to see if there are any patterns revealed.
     
    Last edited: Oct 21, 2012
  9. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    After segment f, next look closely at segment e. It is also very easy.
     
  10. vick5821

    vick5821

    700
    0
    Jan 22, 2012
    I am confuse on what should I do next >< Is the final circuit complicated ? I have to prepare the list of components now ><
     
  11. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    You can't prepare the list of components before you design the circuit.

    You need to express the logic for each segment in terms of the 4 binary input bits as boolean equations (using AND, OR, NAND, NOR, EXOR and INVerter). From that you can construct the circuit and from the circuit you can find the required parts.
     
    Last edited: Oct 23, 2012
  12. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    I will give you one more tip for starters.

    Lokk at this Karnaugh map for segemnt "e":
    [​IMG]

    A, B, C and D are the input variables as shown in your mapping (from left to right). Empty fileds are don't cares because no defined segment state is assigned to these input combinations. So you are free to place a "1" or a "0" in there, whatever suits best. A simple idea is to fill in the row above the "0" with more "0"s. The equation then becomes e=not(A*B) = A NAND B.
    This is your first gate.

    Now do the same for the other segments (apart from "f", which is obvious.

    Harald
     

    Attached Files:

    Last edited: Oct 23, 2012
  13. vick5821

    vick5821

    700
    0
    Jan 22, 2012
    I use 1 as my logic HIGH for the 7 segment ??
     
  14. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    You do know what an inverter is, do you?
     
  15. vick5821

    vick5821

    700
    0
    Jan 22, 2012
    Yes, I know. I mean the table I constructed for each segment is correct ? using 1 to indicate the segment is light up ? By the way , how you get e=not(A*B) = A NAND B for the segment 'e' ? Wondering.
     
  16. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    I calculated for E=0 because that equation can easily be taken from the Karnaugh map. Which is also the answer to your last question: What is the condition for e being "0"? YOu can use the empty fields in the map as you like (either 1 or 0) because these fields do not represent valid input combinations for A...D. So if you fill the column above the lone "0" with zeroes you instantly arrive at the equation. If not, it is time for you to have a look at the principle of Karnaugh maps.

    Whether you need the equation for e=0 or for e=1 also depends on the type of 7-segment display as I have stated in my first answer. Re-read that.
     
  17. vick5821

    vick5821

    700
    0
    Jan 22, 2012
    You do the K-map for the 0 or 1 ? You group the 1 or 0 ??
     
  18. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    neither nor.

    You group the input variables (A to D). Have a look at my post from 10:50 AM. There is a Karnaugh map showing the variables outside the map/grid. I repeat the grid here with some added coloring:
    [​IMG]
    You see the red fields? These are for A=1. All other fileds are for A=0.
    Also the blue fields are for C=1, all other for C=0.
    Where the red and blue fileds intersect, both A and C are "1", therefore the corresponding equation would be A AND B.

    Now do the same yourself. Start with the equation for segment e. I have already given you all necessary hints plus the result. See how to arrive at this result yourself. Then use the same technique for the remaining segments.

    By the way: I really recommend you start with *steve*'s advice and look at segment f. It is really obvious. Get your heaad free and do some around-the-corner thinking. What is the equation for segment f?
    You then have f and e and only 5 more equations to find.

    Check all equations by inputting all possible combinations of input variables (A...D) and verifying the output for each segement against your truth table.

    And by the way: Don't forget to check for the type of 7-segment display (you never answered to that part of my post) and provide suitable series resistors for limiting the current to the display's LEDs.

    If you don't trust your own work:
    I can't promise to be here to check your equations before you have to enter the components list. You may want to include 2 more NAND ICs into your bill of materials. Each IC (e.g. 7400) contains 4 NAND gates. NAND gates are very versatile, they can be used as inverters, you can construct AND gates as well as OR gates or even EXORs from them. So you have some reserve in case your equations turn out wrong.
     

    Attached Files:

    • bla.gif
      bla.gif
      File size:
      1.8 KB
      Views:
      195
  19. vick5821

    vick5821

    700
    0
    Jan 22, 2012
    Huh ? what is this method ? And why the A and B so weird ? Isnt that AB\CD ??
     
  20. Harald Kapp

    Harald Kapp Moderator Moderator

    9,136
    1,844
    Nov 17, 2011
    That's not weird, that's a Karnaugh map. Let me guess: Either you haven't read the linked article from my first post in this thread or you haven't understood it.
    The notation in that article is only slightly different from mine. Instead of marking columns for A and B or C and D respectively, the article uses combinations of AB and CD. But the method is essentially the same. You can replace the separate labels for A and B in my table with the equivalent AB combinations in this sequence (from left to right:
    AB = 00 | 10 | 11 | 01
    and the same goes for CD.

    I definitely don't want to force you to use this method if you are unfamiliar with it. But then you should have learnt at least one other method of synthesizing the logic equations from a truth table. Use whatever method you like.

    It is your homework and not my fault that you try to solve it 5 minutes to 12, so to say.

    Harald
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads
Loading...
Electronics Point Logo
Continue to site
Quote of the day

-