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Signal Strength : pMOS degrades 0 and nMOS degrades 1: why?

Discussion in 'Electronic Basics' started by Mayank Kaushik, Sep 6, 2005.

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  1. Hi,

    I read somewhere that pMOS degrades the logic 0 signal that passes
    through it and nMOS degrades the logic 1 signal that passes through it,
    while they both pass the opposite signals strongly. What is the
    physical property of these devices that gives rise to this behaviour?

    thanks in anticipation,
    Mayank
     
  2. Andrew Holme

    Andrew Holme Guest


    CMOS = Complementary MOS has push-pull outputs, using a pair of transistors
    which can pull the output hard against either power supply rail. NMOS and
    PMOS, in contrast, only have one logic-driven transistor, and a necessarily
    weaker pullup or pulldown that is always on, working against it. The use
    of the word "degrades" is misleading, since it implies a potentially
    cummulative effect, which this is not. It would be better to say they have
    different fan-outs for logic 1 and logic 0.
     
  3. Guest

    Guest Guest

    Not correct.

    The original poster was correct in his description of the
    "problem."

    The physical property that gives rise to that behavior is the
    threshold voltage of the MOSFET.

    A very simplified way of thinking about this is that the MOSFET is
    off if its gate-to-source voltage (Vgs) is less than its threshold voltage
    (Vt.) Suppose you are trying to use an NMOS device as a switch to pass a
    logic 1 (Vdd.) What you are trying to accomplish is having the source
    voltage equal to logic 1, the gate voltage equal to logic 1 (to turn the
    NMOS device on) and the drain voltage equal to logic 1. This MOSFET will
    be off, because Vgs = 0 (Vgate - Vsource = Vdd - Vdd = 0.) In order for
    the MOSFET to bo on, the source voltage must be equal to at most Vdd - Vt.
    This is how the NMOS device will behave if you try to pass a logic 1 (Vdd)
    through it. If you repeat the same exercise with an NMOS device, trying
    to pass a logic 0, you will find that Vgs = Vdd => No problem. Also, if
    you repeat the exercise with a PMOS you will find that a PMOS can pass a
    logic 1 without any Drain-to-Source voltage drop, but not a logic 0. In a
    PMOS device, the source-to-gate voltage must be greater than the absolute
    value of Vt for the device to be on.

    Sorry I didn't have time to give a better explanation, but I'm in
    a hurry. I hope that answers your question, but I'd be happy to answer
    any further questions that you might have.

    Joe

    : Mayank Kaushik wrote:
    :> Hi,
    :>
    :> I read somewhere that pMOS degrades the logic 0 signal that passes
    :> through it and nMOS degrades the logic 1 signal that passes through
    :> it, while they both pass the opposite signals strongly. What is the
    :> physical property of these devices that gives rise to this behaviour?


    : CMOS = Complementary MOS has push-pull outputs, using a pair of transistors
    : which can pull the output hard against either power supply rail. NMOS and
    : PMOS, in contrast, only have one logic-driven transistor, and a necessarily
    : weaker pullup or pulldown that is always on, working against it. The use
    : of the word "degrades" is misleading, since it implies a potentially
    : cummulative effect, which this is not. It would be better to say they have
    : different fan-outs for logic 1 and logic 0.
     
  4. Thanks for the reply, it makes perfect sense now.
    i noticed that ure a PhD student at UT-Austin. Im pursuing an MS in the
    ECE dept (Comp Engg) at UT-Austin.
    regards,
    Mayank
     
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