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Short/Open Detection Link request

Discussion in 'Electronic Basics' started by Roger Bourne, Feb 21, 2006.

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  1. Roger Bourne

    Roger Bourne Guest


    Does anyone know of any good links that explain "design of open/short
    detection" of lead bonds (of IC modules)?

    What would be a good search criteria for google?
    I tried "open/short design detection", "fault detection design" but I
    have yet to find an article which focuses on its design.

    I have my own idea of how to make a open/short detection cct, but its
    mostly derived from the theory section of the manual of [Exatron's
    Open/Short Tester]. It is a small section.

    The dififculty I am having is with the detection of "shorts".
    "Detection of OPEN pins" are RELATIVILYeasy; The ESD diode (that
    protects the pin against ESD) is placed in forward bias in order to
    form a current path --> If there is a current path, then there will be
    a voltage drop accross the ESD diode. If the pin is unconnected (OPEN)
    (e.g. lead bond is broken), then there is no current path. Hence, if
    the pin's voltage is found to be at [~0.6V] or [vdd-0.6] (depends which
    ESD diode is employed for the current path, top or bottom), then the
    pin is NOT open. Otherwise, the pin is open; the pin's voltage will be
    at a rail [vdd] or [gnd].

    The "detection for a SHORTed pin" is not as simple though. As I
    understand it, the method for detecting a short is basically [the
    weighing/measuring of an NOT-open]. In other words if we find that the
    voltage drop of the pin's ESD diode is too low, it would imply that a
    second diode has joined the first one (in parrallel) and as such there
    is a short.
    However, the following problems come to mind:
    1. All the pins of the IC would have to have the same ESD protection.
    Otherwise, the circuit would require trim signals in order for pins
    that are not shorted, not be detected as shorts. Also, some intelligent
    entity (most probably a programmable device) would have to control the
    trim signals with respect to the PUT (pin-under-test). The introduction
    of non-uniform ESD protection renders the short detection fairly
    complicated, at least from a initial point of view. There has to be an
    easier way.
    2. Fairly often, a pin is routed to several IC modules. E.g. A 512Mb
    stick of DDR ram is comprised of several IC modules (if remember
    correcly, there is at 9 SDRAM modules). This poses pretty much the same
    problem as in 1. Some pins of the 512Mb stick will only be routed to 1
    pin on 1 IC module (e.g. data signals), while others are/should/might
    be shared (e.g. SELECT signals of the SDRAMs). This pin sharing will
    multiply the ESD protection.
    3. Assuming that all pins have the same ESD protection, how is the
    "expected voltage drop of the ESD diode" to be saved, in order to be
    used as a reference? Which pin will be used during the saving process?
    How can it be assured that the pin will not have a short?
    4.If the process is rendered automated, are there any provisions one
    has to take to assure a more less speedy outcome?

    Any help will be appreciated.

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