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Shared clock and data pins

Discussion in 'Electronic Basics' started by David Harper, Nov 7, 2004.

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  1. David Harper

    David Harper Guest

    I'm relatively new to A/D converters and such, and was wondering if I
    can put two or more A/D converters on the same clock and/or data out
    lines, while leaving the CS pins on different lines? Or maybe sharing
    the CS and clock pins, leaving the data out lines separate?

    My goal is to minimize pin use on the microcontroller.

    Thanks in advance!
  2. Yes, no problem. If you separate the data-out you can sample
    both ADC's at the very same moment, which may be an advantage.
    It could also be a bit faster, you only need to bitbang the
    clock once for two DAC's being sampled at the same time.
  3. John Larkin

    John Larkin Guest

    If it's SPI, you can common the clock and data lines, and have
    separate CS- decodes. If you do hang a lot of loads on the clock,
    beware of ringing... terminate at the end of the run, or at least
    leave a hook. Use an external CS decoder (HC138, whatever) if you're
    really hard up for pins.

    Or you could read them out simultaneously (into an FPGA, for example)
    by splitting only the data lines.

  4. john jardine

    john jardine Guest

    For least pin use it's generally much better to use a multi input A/D chip
    that has channel switching built in. Eg ... 8 channels, 12 bit, serial
    (cheap!), such as the Microchip type MCP3208. You've 8 seperate voltage
    inputs to play with but only need 4 micro' pins allocating to drive the
  5. You presumably speak of converters with SPI interface. In this case,
    yes, you can share the clock and data pins. Just to be sure, check
    whether the converter tri-states the data pin while its CS line is
    inactive. If it is really SPI compatible, it should do this, but if not,
    you may have to add additional buffers.

    You can also share CS and clock pins while keeping the data pin
    separate. In this case tri-stating the data pin isn't necessary. The
    downside is that you can only read all ADCs simultaneously.

    If you use ADCs with a parallel output bus, you can also share the data
    lines if they are tri-stated while CS is inactive.
  6. The CLK line is an output from your micro and an input to all the serial ADCs,
    so that can be wired in common. The DATA lines are outputs from the serial ADCs
    and that's a problem. You can either wire the DATA lines to separate pins on
    the micro or else check to see if the DATA line goes tristate if the CS line is
    inactive. If so, then wire them in common as well and just don't drive two CS
    lines active at once. The CS lines will need to be on separate lines to the
    micro. If you have more than a few ADCs you can use a binary decoder, like the
    74LS138 or the 74LS154, to reduce micro pin count at the expense of another IC.

  7. Most multi-input ADCs use a common reference voltage, I believe. That may (or
    may not) be a problem. Also, even in the better cases (if memory serves)
    isolation is usually not better than 80db between the inputs and too often less
    than that. For 12-bit, it again may or may not be a problem. But for 16-bit it
    may be an issue.

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