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SG/UC3525 problem resolved

Discussion in 'Electronic Design' started by Pooh Bear, Jun 25, 2005.

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  1. Pooh Bear

    Pooh Bear Guest

    Thanks to everyone who contributed to the previous thread concerning my
    mismatched timing periods with this PWM smps chip.

    The culprit was indeed the shutdown pin.

    I see now what happened.

    I followed the guide to use of the shutdown pin in the 'lab test
    fixture' diagram. The *only* diagram in fact that shows it's use.

    That shows shutdown activated by connecting the shutdown input to Vref
    via a 2k resistor. To *enable* normal operation the pin is open ( indeed
    it's connected to the 2k resistor which is now floating ) - which the
    text says contradictorily earlier that you shouldn't do !

    Some bright person spotted that a recent copy of a TI data sheet
    correctly shows the shutdown input tied to Vref by a resistor ( 5K for
    some reason in this case ) and the chip enabled by *shorting shutdown to
    ground* !

    I perused many data sheets including TI, STM, Motorola, On-semi's
    version of same and *all* make the same mistake of showing pin 10
    floating in active mode. Only a recent data sheet for TI's 3525A gets it
    right - even the data from TI for the 3525B enhanced version gets it
    wrong again *and* an earlier rev of TI's 3525A also shows the wrong
    method !

    Can you believe that ?

    Just to make things more interesting the internal block diagram of the
    3525 in 'lab test fixture' mode is different to the one given earlier in
    the data sheet and gives an erroneous impression of how shutdown is
    internally connected and how it functions - see the connection to the
    PWM latch. This error is replicated in *all* the data sheets I've seen
    including the one with the correct pin connection !

    Phew !

    Thanks to all for sorting that one for me.

    Shorting shutdown to ground to enable operation avoids the noise pickup
    of course.


    Cheers, Graham
     
  2. kell

    kell Guest

    Agree on all fronts. 3525 data sheets all copy each other, and they
    suck. And I had the same hassle figuring out I had to ground pin 10...
     
  3. Mac

    Mac Guest

    Thanks for following up with the resolution. I'm sure it will save some
    other people a lot of trouble when they have a similar problem and search
    google groups. ;-)

    --Mac
     
  4. Pooh Bear

    Pooh Bear Guest

    YVW ! The least I could do.
    I'm actually intending to contact all the relevant semiconductor vendors and
    request they amend their data sheets ( with a *big* erratum message ).

    Graham
     
  5. legg

    legg Guest

    The UC3525A data sheets were generated in the mid 80s, to illustrate a
    replacement part for Silicon General's SG3525 (already obsolescent at
    that time) and SG3525A. Your 'correct' lab bench test shutdown
    hook-up method shows up in the earliest 'A' version Unitrode data
    sheets, which TI adopted.

    The 3525B appeared in the mid-90s. As the B version only represented
    a process-tightening, I doubt that there was any great effort to
    generate app notes in excess of those already present (eg U89 last
    published in IC500 in '87).

    The shut-down pin in Unitrode A and B versions was usable as a crude
    high speed latch in pulse-by-pulse limiting. As such it presented
    application advantages over the 3524 and 3525, which were either slow,
    unlatched, or both.

    Lab bench open-loop test layout is intended only for that function,
    and both will probably work as described, to demonstrate the improved
    features. I note that this part's sheet was last revised in '04, but
    most likely only to ease electronic publication and storage.

    Most power supply designers will become aware, fairly early on, that
    noise immunity is improved when localized low impedances are provided
    in victim locations - this includes all IC input pins. Open circuit
    input pins are seldom a good idea in a noisy environment.

    You have discovered one of the advantages that accurate physical
    breadboards display over electronic simulations.

    RL
     
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