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Seven segment display decoding

Discussion in 'Electronics Homework Help' started by pjmoriarty, Nov 14, 2013.

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  1. pjmoriarty

    pjmoriarty

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    Nov 14, 2013
    I'm currently working on a way of decoding a seven segment display in order to produce a 1-6 range on the display. I have the circuit designed and working. However, I know for a fact that it is not at all optimal. I was wondering if any of you could help me with my design?

    I have included my current design. I only want to use logic gates in the design, preferably only inverters and two input gates.

    Thank you for any help ( I accidentally uploaded this to the Circuit help section before I saw this forum. I'm not looking for an answer, just a kick in the right direction) :)
     

    Attached Files:

  2. Laplace

    Laplace

    1,252
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    Apr 4, 2010
    So what does your truth table and Karnaugh map look like for each segment?
     
  3. pjmoriarty

    pjmoriarty

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    Nov 14, 2013
    Here are my original K-Maps & drawing of the circuit with a truth table. Sorry about how messy it is, i'm really not the best at neatness.
     

    Attached Files:

  4. Laplace

    Laplace

    1,252
    184
    Apr 4, 2010
    Here is what I would try for minimization. For display of the numbers 1-6 the values of 0 & 7 become don't-care conditions.
     

    Attached Files:

  5. pjmoriarty

    pjmoriarty

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    Nov 14, 2013
    The display I'm using is active low so those kmaps are just the opposite of the ones I've done
     
  6. Laplace

    Laplace

    1,252
    184
    Apr 4, 2010
    I prefer doing the K-maps using positive logic, then making the switch to negative logic when selecting the NAND & NOR gates to use. It's less confusing that way.
     
  7. Laplace

    Laplace

    1,252
    184
    Apr 4, 2010
    Here is an example of working through the entire process. There is not single correct optimized solution because the optimization might be to minimize the number of gates, or minimize the number of packages, or take advantage of inputs and their inverse, e.g., from a flip-flop, being available. For this example I chose to optimize by using only NOR gates. With the K-map, select minimizations from the ones, and then for good measure minimize zeroes with negation. Convert each segment minimization to Boolean algebra. Then draw a gate implementation using positive logic from the previous one/zero minimization, adding inversion circles (green) for negated inputs and active low outputs, then add inversion pairs to create NAND/NOR gates with as few inverters as possible. It may be necessary to do gate optimization for both one & zero logic minimizations for each segment to see which gives the best result. Draw the gate logic again using NAND/NOR logic in final form. As a final check convert the NAND/NOR logic to spreadsheet logic functions and test the truth table. One can even select spreadsheet cells in the form of a figure eight, and use conditional formatting to 'illuminate' the display when driven by the C-B-A binary inputs, as shown in the Libre Office .ods spreadsheet attachment.

    [​IMG]
     

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