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Series Termination

Discussion in 'Electronic Design' started by [email protected], Feb 21, 2009.

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  1. Guest

    I am trying to understand series termination for a board I'm designing
    with a Cyclone II FPGA. The Cyclone II has internal series termination
    resistors making it easier for me. These resistors are typical 50 ohms
    (25 in some cases). I assume the traces on my board must also be a 50
    ohm transmission line so I plug some numbers into a microstrip trace
    impedance calculator (at http://www.chemandy.com/calculators/microstrip-transmission-line-calculator-hartley27.htm
    using specs for the board from http://www.expresspcb.com/ExpressPCBHtm/SpecsStandard.htm)
    and it says I need a trace that is 1.5 mm wide. That trace is too
    wide...it'll cover three pins! I think I must be missing something
    because when I look at a PCB I don't see traces this wide for data.

    Thanks for your help,
    Brian
     
  2. Tim Williams

    Tim Williams Guest

    How thick is your PCB? Does it have enough layers? That'll take down
    thickness-per-layer pretty well.

    Tim
     
  3. Baron

    Baron Guest

    Use whatever trace impedance suits, then terminate to match. 1.5mm is
    about right for 50ohms on 1oz FR4. But do you have to use 50ohm ?
    Could you use, say 300ohm ? Without some knowledge of your requirement
    its difficult to make sensible suggestions.
     
  4. WhiteDog

    WhiteDog Guest

    Hi Brian,


    Don't get too hung up on 50 ohms unless you REALLY need it (like when
    you are doing a board using RF parts that are internally matched to 50
    ohms). The place to start is with the signals you are sending down the
    traces. How fast are the edges? 1ns? 500ps? faster?

    This tells you the bandwidth requirement of your design, and what the
    electrical length of your transmission lines will be. Depending on how
    far apart your chips are, you may not need to be worried about
    matching. Remember, driving a 50 ohm line requires a nontrivial
    amount of current from the driving devices. I like the suggestion of
    300ohms (or somewhere in between). It typically works better on FR4.

    Tell us more about the project... we'll be able to help you a little
    easier. I've done several designs with the Cyclone II, and have seldom
    used 50ohm terminations with anything other than fast serial data
    (over 100Mbps), clocks that I need to be really pure (for DSP) or
    stuff that interfaces to OTHER chips that require 50-ohm lines.
     
  5. Baron

    Baron Guest

    I agree its close to 377ohms ! Depending upon frequency, quite
    practical.

    The points being 1/ does the OP need to use 50ohms, and 2/ Without some
    knowledge of the requirements it is difficult to make sensible
    suggestions.
     
  6. Guest

    Wow,I didn't expect so much help. Thank you so much.

    I took a while to respond because I wanted to do some more research to
    ask less stupid questions (hopefully).

    The advice you all gave helped a lot. First I was getting "hung up" on
    50 ohms. I assumed the FPGA provided 50 ohm series terminating
    resistors for a reason, and that I needed to take advantage of it.
    Also I wanted to use a two layer FR4 board to reduce cost (it's my
    personal project) but after getting deeper into the layout it became
    too much of a burden, so I opted for a 4 layer board. This greatly
    reduced the trace width necessary for a particular transmission line.

    If I am reading the Cyclone II handbook correctly, the rise and fall
    times are 500 ps, giving an electrical length of 144 mm. This means
    that, according to this article http://zone.ni.com/devzone/cda/tut/p/id/3854
    , I only need to consider the traces as transmission lines if the
    length exceeds about 2.5 cm. That's good to know...

    How about some background? I'm trying to build a 900 MHz CDMA
    transmitter and receiver, with a 1 Mcps chip rate (actually 1.023
    Mcps, more on that later). I've posted a block diagram of the
    transmitter here: http://www.geocities.com/heiligb/LPS/transmitter_block_diag.gif

    The schematic diagrams so far are here: http://www.geocities.com/heiligb/LPS/transmitter_schem1.gif
    and here: http://www.geocities.com/heiligb/LPS/transmitter_schem2.gif

    So far there is no useful output from the FPGA, only LEDs and GPIOs
    for debugging.

    The plan is the FPGA will generate the chipping code, combine it with
    the data from USB, and send it to the mixer at zero IF. It is then
    mixed up to 920 MHz, filtered and amplified as necessary (haven't done
    much design there yet) and transmitted. My plan of attack is to
    approach the design incrementally, creating about 5 boards and testing
    along the way. Since this is my first high-speed or wireless board
    design I believe I'll ultimately save money (and understand the design
    better) this way as opposed to creating a full design and having it
    not work. The first board will only have the DAC output sent to an SMA
    connector. I'm also assuming I'll be able to get my hands on a
    spectrum analyzer, high-speed O-scope, etc for testing. Haven't solved
    that problem yet.

    It seems to me that the requirement for decoupling capacitors can be
    summarized as (somewhat tongue in cheek): put a capacitor as close to
    the pin as possible. Make the capacitance as large as possible and the
    size as small as possible, with a good temperature coefficient,
    balancing the cost of the cap.

    Here are some highlights from the design so far:
    I copied lots of examples from other designs.
    I put a .1 uF capacitor on every DC input pin of the FPGA. I don't
    know if this is overkill (or underkill?) but it seems like it can't
    hurt. The decoupling caps for the FPGA are on page 1.
    The decoupling caps on VCCA_PLL1 and VCCA_PLL2 came from an Altera
    reference design. Can't figure out why all those different caps would
    help, but what do I know?
    The LEDs I ordered (Part# 754-1127-1-ND) have a voltage rating of 2.1
    volts and a current draw of 20ma. I took (Vcc - VLED) / ILED and found
    I needed a 60 ohm resistor. Digikey didn't have one so I got 62 ohms
    instead.
    I assumed a max of 500ma for 1.2v and 500ma for 3.3v is enough. I put
    the jumper there so I can test the current draw in case I assumed
    incorrectly.
    I'm using only JTAG to program the chip. I ordered a knock-off USB
    Blaster from China (hope I don't get ripped off) and hope to get
    Quartus II software for a reasonable price.

    What's next?
    The output of the FPGA will be a square wave at 1 Mcps with no IF. I'm
    not convinced yet that I can't directly take an output pin from the
    FPGA, send it through a DC blocking capacitor directly to the mixer
    (as an analog signal) bypassing the DAC. For this reason I want to
    take one pin, terminate for 50 ohms, put a series cap and output it to
    an SMA connector. I want to see what comes out on the spectrum
    analyzer.
    Assuming that doesn't work I will also send data and clock to an 8-bit
    DAC (such a waste to have 8 bits when I only need one!). The output of
    that will also be to an SMA connector so I can see how it looks.

    I've been researching the DAC and I don't know how to pick one. There
    are two kinds: current-output and voltage-output. I try to understand
    what a current output is and how it is different from a voltage
    output, but I can't understand and I can't find any reference. If the
    output impedance is constant, then an increase in current will result
    in a proportional increase in voltage, right? So then what's the
    difference?

    Sorry for the long post. Read as much as you like and respond as much
    as you like. Again I greatly appreciate your help.
     
  7. Guest

    I missed two points in my post:

    It is a BPSK transmitter.

    With a 10 MHz input I couldn't figure out how to get a 1.023 Mhz clock
    using only the FPGA PLLs. So, when I get to that point if I still
    can't figure out how to generate the clock I'll either add an external
    PLL or eliminate the requirement. The code sequence length is 1023
    chips and it would be nice if the code repeated every ms, but that's
    not necessary.

    Thanks again!
     
  8. Baron

    Baron Guest

    wrote:

    Notes inline.
    If there are any example board layouts based around the chips you are
    using it might be worth a look.
    Any trace or piece of wire can be considered a transmission line ! The
    shorter it is with respect to frequency the less its effect is going to
    be ! A general rule of thumb would be if its 10% or less of a wave
    length it can be neglected.
    920Mhz = A wavelength of 326mm
    One of the things you will have to be careful of is creating resonant
    loops with multiple caps on the supply lines. Also the caps themselves
    have self resonances ! Whilst they should be orders of magnitude
    higher than the frequencies that you are playing with. Its worth
    checking them.

    I could relate an experience here... Maybe later.
    See note above.
    I think you will find that you can reduce the current draw for that LED
    considerably and it will still be bright enough. I would run it around
    5 to 10ma.
     
  9. krw

    krw Guest

    Sounds about right.
    Any trace or wire *can* be, but it often isn't necessary to consider
    it a t-line. Where the effect becomes apparent has nothing to do with
    the wavelength, rather the edge rates. The general rule-o-thumb is if
    the length of the line is 1/2 the edge rate (round trip = edge) then
    the line will look like a transmission line. Shorter than that it's
    more like a lumped capacitor.

    <snip>
     
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