serial interface

[michael]

Hello there,

I am working on a FPGA project that requires to interface the FPGA with
an array of serial 12bit DAC. I can not use parallel 12bit DAC simply
because I don't have enough pin counts on that FPGA (360 pins are
needed if use parallel DAC). So I plan to write a synchronized serial
interface (clk, data, sync) to pump the data out as soon as the 12bit
data is generated inside FPGA. I image that I probably need a shift
register, PLL ( generate clocks for both shift register and the DACs),
a bit counter to signal the end of transmit? Does anyone have the
experience to do this? Please help.

Thanks

Mike

 

[Peter Bennett]

Hello there,

I am working on a FPGA project that requires to interface the FPGA with
an array of serial 12bit DAC. I can not use parallel 12bit DAC simply
because I don't have enough pin counts on that FPGA (360 pins are
needed if use parallel DAC). So I plan to write a synchronized serial
interface (clk, data, sync) to pump the data out as soon as the 12bit
data is generated inside FPGA. I image that I probably need a shift
register, PLL ( generate clocks for both shift register and the DACs),
a bit counter to signal the end of transmit? Does anyone have the
experience to do this? Please help.

I've just done that on an Altera MAX II CPLD to read a MAX1202 ADC.
No PLLs involved - but I have an external crystal oscillator to
provide a 1 MHz clock to the SPI circuit. It uses a couple of
counters and a shift register. If you email me at
bennett(at)triumf.ca, I'll send you a .pdf of the schematic on Monday.

--
Peter Bennett, VE7CEI
peterbb4 (at) interchange.ubc.ca
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