Andrew Crook said:
sorry i meant asynchronous sequential logic. I think this means that the
cicuits work at there own speed and not that of a clock.
Andi
Andi,
There's much to say about sequential logic. Many thick books are written
about it. So the next is short and far from complete. Nevertheless:
Sequential logic uses memory elements usually flipflops. As we speak about
binary elements, the number of combinations that can be made is 2^n in which
n is the number of memory elements. In sequential circuits each combination
of outputs of the flipflops is known as a state. The flipflops along with
the controlling logic is known as a state machine.
State machines are always in some state. They change state on the changing
of an input signal. When the input signal(s) are randomly changing and the
state machine acts on it immediately, we use to name them asynchronous. This
type of sequential circuits has its use. You may think of asynchronous
counters for instance. Sometimes when component count or speed are critical
they may be the only choice. After all, flipflops are asynchronous
internally. Designing reliable asynchronous circuits however is a pain.
Especially when you have more then one randomly changing input signals,
asynchronous circuits quickly become uncontrollable. Like I mentioned, the
state machine changes state on the changing of an input signal. But this
changing of state takes some time and when the circuit receives a new change
of an inputsignal during this time, the outcome becomes unpredictable.
To overcome many of the problems of the asynchronous circuits, synchronous
circuits are used. All flipflops get a clock input and all clock inputs get
one and the same clock signal. Changing of the state is restricted to the
active edge of the clock. So the influence of input changing on the state
machine is now delayed until the next active clock edge. A problem may
still arise when an input changes during this active clock edge. To most
simple way to overcome this problem is to synchronize the inputs. Simply add
an extra D-flipflop to the circuit. This flopflop has nothing to do but
receiving an input signal make it available for the state machine. When an
active clockpulse and an input signal occurs at about the same time, the
input may come through at this clock edge or at the next one, but the state
machine always get a synchronised input signal. (In very critical situations
you even have to use two D-flipflops to synchronize reliably but that's
beyond this short story.)
So to design a synchronous circuit you start to make a state diagram or a
state table. Make sure you define a transition from every possible state.
Also make sure you account for every possible input combination at every
state. There are technics to reduce the number of states if possible. Once
you have done this you know the minimum number of flipflops required and you
can use k maps to find the controlling logic. You will also need a clock
generator of course but its design highly depends on the circumstances.
petrus
