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secondary turn-on

  • Thread starter Anthony C Smith
  • Start date
A

Anthony C Smith

Jan 1, 1970
0
Hi I am using the HIP4081 driving a H bridge with 4 STP24NF10 fets-
Gate resistors are 10R in high side fets, 33R in low side, all drive R's
have 1n4148 discharge diodes to speed turn off-
circuit functions well -except for a 5n pulse on the low fet coincident with
the turn on of the high fet- PCB is layed out to full guidelines from harris
including laying gate traces with source feed on underside as plane to
reduce the chance of this phenomina-

any usefull ideas on reducing this- unit works well but this is obviously
wasting power and heating the low side fet (although even without sink its
mostly cold)

Regards

Anthony C Smith
 
W

Winfield Hill

Jan 1, 1970
0
Anthony C Smith wrote...
Hi. I am using the HIP4081 driving a H bridge with 4 STP24NF10
fets- Gate resistors are 10R in high side fets, 33R in low side,
all drive R's have 1n4148 discharge diodes to speed turn off ...

Whoa! The HIP4081 can source/sink several amps to the FET gates,
far too much for wimpy '4148 diodes. For fast turnoff you want
to keep the sink-path voltage drops as low as possible; so use
1n5817 Schottky diodes. Also, along the same vein of thought,
never use logic-level FETs in an application like this. I made
that mistake ... once.
 
A

Anthony C Smith

Jan 1, 1970
0
Winfield Hill said:
Anthony C Smith wrote...

Whoa! The HIP4081 can source/sink several amps to the FET gates,
far too much for wimpy '4148 diodes. For fast turnoff you want
to keep the sink-path voltage drops as low as possible; so use
1n5817 Schottky diodes. Also, along the same vein of thought,
never use logic-level FETs in an application like this. I made
that mistake ... once.
thanks for the input-
Can you reccommend any decent fets for the job? switching frequency is
384KHz, power is 200W into 1R @32V max, 22V min the H bridge drives a 40u
common mode choke followed by a 3rd order butterworth filter at 50KHz
regards
Anthony
 
A

Anthony C Smith

Jan 1, 1970
0
Winfield Hill said:
Anthony C Smith wrote...

Whoa! The HIP4081 can source/sink several amps to the FET gates,
far too much for wimpy '4148 diodes. For fast turnoff you want
to keep the sink-path voltage drops as low as possible; so use
1n5817 Schottky diodes. Also, along the same vein of thought,
never use logic-level FETs in an application like this. I made
that mistake ... once.

I just checked the data- original design used RFP22N10 fairchild devices-
this ST part was the nearest equivalent, but with better (lower) rds on and
a lower gate charge- gate threshold voltage is the same 2-4V- the lower gate
charge reduced the quiecent current of the amp- which is good as it has to
run on batteries for backup.
while searching I found a p fet optimised for Cgs/Cdg of 0.7 to minimise
secondary turn on- has anyone used additional gate C to prevent this?
regards
Anthony
 
W

Winfield Hill

Jan 1, 1970
0
Anthony C Smith wrote...
Winfield Hill wrote ...

I just checked the data- original design used RFP22N10 fairchild
devices- this ST part was the nearest equivalent, but with better
(lower) rds on and a lower gate charge- gate threshold voltage is
the same 2-4V- the lower gate charge reduced the quiecent current
of the amp- which is good as it has to run on batteries for backup.
while searching I found a p fet optimised for Cgs/Cdg of 0.7 to
minimise secondary turn on- has anyone used additional gate C to
prevent this?

I doubt that's your problem, not if you were to use Schottky pulldown
diodes to control the off FET's anyway. Did you provide a delay using
the '4081 HDEL and LDEL resistors (pins 8, 9) to prevent shoot-through?
 
F

Fritz Schlunder

Jan 1, 1970
0
Anthony C Smith said:
Hi I am using the HIP4081 driving a H bridge with 4 STP24NF10 fets-
Gate resistors are 10R in high side fets, 33R in low side, all drive R's
have 1n4148 discharge diodes to speed turn off-
circuit functions well -except for a 5n pulse on the low fet coincident with
the turn on of the high fet- PCB is layed out to full guidelines from harris
including laying gate traces with source feed on underside as plane to
reduce the chance of this phenomina-

any usefull ideas on reducing this- unit works well but this is obviously
wasting power and heating the low side fet (although even without sink its
mostly cold)

Regards

Anthony C Smith


If the little pulses are large enough to cause dV/dt induced cross
conduction (have you actually measured the cross conducting current, or have
you merely observed small less than threshold blips appearing on the low
side MOSFET gates?), then there are a number of things you might try.

This document:

http://focus.ti.com/lit/ml/slup169/slup169.pdf

Would have you believe the gate resistor paralleled with diode only provides
incremental improvement over just the gate resistor alone (see figure 12 and
related text in the document). From my personal experience with dV/dt
induced cross conduction I would tend to agree. The document claims the
circuit of figure 13 is superior. I tend to agree, but I think the best
solution would be if MOSFET gate driver IC manufacturers provided two
separate pins for each gate drive output. One pin for sinking current and
one pin for sourcing current. That way you could use separate valued gate
drive resistors for sinking and sourcing. It seems in most power MOSFET
applications (especially true in H-bridges) turn on should be a fair amount
slower than turn off for optimal performance.

In addition to trying the circuitry of figure 13 you might also consider
applying negative gate drive, or perhaps keeping the same circuit you are
currently using (gate resistor in parallel with diode) but increasing the
upper MOSFETs' gate resistor values. If cross conduction really is
occurring, this can sometimes dramatically reduce total MOSFET heating even
though it makes turn on slower. Of course, this isn't optimal from a
performance standpoint since you probably want really fast turn on and turn
off without any dV/dt induced cross conduction, but sometimes the added gate
drive complexity may not be worth it (especially since fast turn on/off
worsens the EMI situation).
 
A

Anthony C Smith

Jan 1, 1970
0
-snip-
I doubt that's your problem, not if you were to use Schottky pulldown
diodes to control the off FET's anyway. Did you provide a delay using
the '4081 HDEL and LDEL resistors (pins 8, 9) to prevent shoot-through?
Using 68K for HDEL and LDEL- using the DSO I can see the delay so this is
not the problem- I also increased the values to no avail- I am trying the
diodes now
Regards
Anthony
 
A

Anthony C Smith

Jan 1, 1970
0
Fritz Schlunder said:
-snip-

If the little pulses are large enough to cause dV/dt induced cross
conduction (have you actually measured the cross conducting current, or have
you merely observed small less than threshold blips appearing on the low
side MOSFET gates?), then there are a number of things you might try.

No I have measured the current -5ns 50A flowing hence wanting to remove it!

Thanks for the link most useful
Would have you believe the gate resistor paralleled with diode only provides
incremental improvement over just the gate resistor alone (see figure 12 and
related text in the document). From my personal experience with dV/dt
induced cross conduction I would tend to agree. The document claims the
circuit of figure 13 is superior. I tend to agree, but I think the best
solution would be if MOSFET gate driver IC manufacturers provided two
separate pins for each gate drive output. One pin for sinking current and
one pin for sourcing current. That way you could use separate valued gate
drive resistors for sinking and sourcing. It seems in most power MOSFET
applications (especially true in H-bridges) turn on should be a fair amount
slower than turn off for optimal performance.

In addition to trying the circuitry of figure 13 you might also consider
applying negative gate drive, or perhaps keeping the same circuit you are
currently using (gate resistor in parallel with diode) but increasing the
upper MOSFETs' gate resistor values. If cross conduction really is
occurring, this can sometimes dramatically reduce total MOSFET heating even
though it makes turn on slower. Of course, this isn't optimal from a
performance standpoint since you probably want really fast turn on and turn
off without any dV/dt induced cross conduction, but sometimes the added gate
drive complexity may not be worth it (especially since fast turn on/off
worsens the EMI situation).
Thats why I have the different values on upper/lower halves of the bridge-
this reduced ringing to virtually nothing and boosted performance
 
W

Winfield Hill

Jan 1, 1970
0
Anthony C Smith wrote...
No I have measured the current -5ns 50A flowing...

How did you make this measurement (keep in mind L dI/dt)?
 
A

Anthony C Smith

Jan 1, 1970
0
Winfield Hill said:
Anthony C Smith wrote...

How did you make this measurement (keep in mind L dI/dt)?

It measures as a 0.75V peak pulse across a 0R015 non inductive sense
resistor between the bottom of the bridge and true ground- both paths are
less than 5mm long and over 5mm wide to avoid skin effect problems
regards
Anthony
 
F

Fritz Schlunder

Jan 1, 1970
0
Anthony C Smith said:
It measures as a 0.75V peak pulse across a 0R015 non inductive sense
resistor between the bottom of the bridge and true ground- both paths are
less than 5mm long and over 5mm wide to avoid skin effect problems
regards
Anthony


Your so called non-inductive sense resistor is still inductive. I'm not
sure what you mean by 5ns 50A, but suppose a current rise time from 0-50A in
5ns. This suggests a dI/dt of 10,000,000,000 Amps/second. So how much
inductance would produce 0.75V with that kind of current ramp? Well,
E=L*dI/dt, so in other words a mere 75 picoHenries would produce 0.75V with
such a high current ramp rate. Given a vague rule of thumb of around 1nH
per millimeter of trace length, it is very probable your "non-inductive"
resistor has way more than 75pH of inductance (no matter its actual
construction). Additionally it would be necessary for your scope probe to
be connected impractically close to the resistor to avoid including 75pH of
inductance in the measurement.

So the basic idea is it is difficult to actually measure the cross
conduction current with any reasonable expectations of accuracy. By the
sounds of it you probably are getting cross conduction, but it is probably
not as severe as you think it is.
 
A

Anthony C Smith

Jan 1, 1970
0
Fritz Schlunder said:
Your so called non-inductive sense resistor is still inductive. I'm not
sure what you mean by 5ns 50A, but suppose a current rise time from 0-50A in
5ns. This suggests a dI/dt of 10,000,000,000 Amps/second. So how much
inductance would produce 0.75V with that kind of current ramp? Well,
E=L*dI/dt, so in other words a mere 75 picoHenries would produce 0.75V with
such a high current ramp rate. Given a vague rule of thumb of around 1nH
per millimeter of trace length, it is very probable your "non-inductive"
resistor has way more than 75pH of inductance (no matter its actual
construction). Additionally it would be necessary for your scope probe to
be connected impractically close to the resistor to avoid including 75pH of
inductance in the measurement.

So the basic idea is it is difficult to actually measure the cross
conduction current with any reasonable expectations of accuracy. By the
sounds of it you probably are getting cross conduction, but it is probably
not as severe as you think it is.
Thanks for the explaination- I am trying to fix a problem on a current board
any patch ideas? this is driving me up the wall- I was trying to lower the
THD and this spike is everywhere to some extent
reagrds
Anthony
 
T

Terry Given

Jan 1, 1970
0
Anthony said:
Thanks for the explaination- I am trying to fix a problem on a current board
any patch ideas? this is driving me up the wall- I was trying to lower the
THD and this spike is everywhere to some extent
reagrds
Anthony

Hi Anthony,

A perhaps stupid question - is what you are seeing actually gate
current? If possible, re-route the lower FET gatedrive such that gate
charge and discharge current does not flow thru the sense resistor (easy
to do if you have a separate power gnd on the smps chip, or a transistor
buffer).

Cheers
Terry
 
L

legg

Jan 1, 1970
0
Thanks for the explaination- I am trying to fix a problem on a current board
any patch ideas? this is driving me up the wall- I was trying to lower the
THD and this spike is everywhere to some extent

You could increase the upper fet gate current turn-on limiter. You
obviously have incremental values to play with before you hit the same
value used on the lower part.

You haven't yet indicated whether the use of schottkies did anything
to your measurements.

RL
 
W

Winfield Hill

Jan 1, 1970
0
Fritz Schlunder wrote...
Anthony C Smith wrote ...

Your so called non-inductive sense resistor is still inductive. I'm not
sure what you mean by 5ns 50A, but suppose a current rise time from 0-50A
in 5ns. This suggests a dI/dt of 10,000,000,000 Amps/second. So how
much inductance would produce 0.75V with that kind of current ramp?
Well, E=L*dI/dt, so in other words a mere 75 picoHenries would produce
0.75V with such a high current ramp rate. Given a vague rule of thumb
of around 1nH per millimeter of trace length, it is very probable your
"non-inductive" resistor has way more than 75pH of inductance (no matter
its actual construction). Additionally it would be necessary for your
scope probe to be connected impractically close to the resistor to avoid
including 75pH of inductance in the measurement.

Thanks, Fritz, for making my point so eloquently. Anthony's inductance
will no doubt be much more than 75pH, or even 10nH. For example, power
MOSFET internal lead wiring is typically 5 to 10nH. If we assume 5nH
total, a 0.75V drop implies a slow 150mA/ns current rate-of-change.
So the basic idea is it is difficult to actually measure the cross
conduction current with any reasonable expectations of accuracy. By
the sounds of it you probably are getting cross conduction, but it is
probably not as severe as you think it is.

It's not clear Anthony is seeing shoot-through currents; there are many
other sources of impulse noise during switching that may be visible at
the FET's source lead. For example, the high capacitive gate currents
go through that path. One insidious severe noise source comes from fast
current snap-off in the FET's substrate diode after its reverse-recovery
time is finished. The primary way to tell this is happening is presence
of severe switching noise. This situation will arise whenever the FET
is off and its diode is made to conduct, say caused by flyback from the
inductance in Anthony's output filter, "H bridge drives a 40u common mode
choke followed by a 3rd order Butterworth filter at 50kHz." In extreme
cases the source-voltage bounce can be severe enough to damage the FET by
(internally) exceeding its gate-voltage limit for a few ns. This I know
from sad experience, and from careful measurement with my superior probes
(I mention probes, because its VERY easy to be mislead when taking such
measurements, e.g. move the probe over to ground on the other side of the
sense resistor and observe the zero-volt signal... and ditto elsewhere).
 
A

Anthony C Smith

Jan 1, 1970
0
Terry Given said:
Hi Anthony,

A perhaps stupid question - is what you are seeing actually gate
current? If possible, re-route the lower FET gatedrive such that gate
charge and discharge current does not flow thru the sense resistor (easy
to do if you have a separate power gnd on the smps chip, or a transistor
buffer).

Its definately secondary turn on, albiet maybe smaller than I first thought
the above is not realy practical as its not a smps, its a discreet modulator
driving the HIP for an audio amplifier and the sense resistor is part of the
I limit system.
regards
 
A

Anthony C Smith

Jan 1, 1970
0
legg said:
On Mon, 6 Dec 2004 09:22:18 +0000 (UTC), "Anthony C Smith"


You could increase the upper fet gate current turn-on limiter. You
obviously have incremental values to play with before you hit the same
value used on the lower part.

I have been trying this and it appears to be working
You haven't yet indicated whether the use of schottkies did anything
to your measurements.

Strangely they did not improve things
thanks for the input
 
A

Anthony C Smith

Jan 1, 1970
0
Winfield Hill said:
It's not clear Anthony is seeing shoot-through currents; there are many
other sources of impulse noise during switching that may be visible at
the FET's source lead. For example, the high capacitive gate currents
go through that path. One insidious severe noise source comes from fast
current snap-off in the FET's substrate diode after its reverse-recovery
time is finished. The primary way to tell this is happening is presence
of severe switching noise. This situation will arise whenever the FET
is off and its diode is made to conduct, say caused by flyback from the
inductance in Anthony's output filter, "H bridge drives a 40u common mode
choke followed by a 3rd order Butterworth filter at 50kHz."
I think I am getting to the problem- not quite where I thought it was,
the bridge is a phase shift type, with 0V in both bridges have a common mode
switching frequency, and switch together, +v one bridge duty cycle
increases, the other decreases,-v the opposite.
By removing the load and applying a DC offset it appears that the pulse is
comming from the oposite bridge half, and appears to be from the half under
measurement when at 0V or small signal input.
cases the source-voltage bounce can be severe enough to damage the FET by
(internally) exceeding its gate-voltage limit for a few ns. This I know
from sad experience, and from careful measurement with my superior probes
(I mention probes, because its VERY easy to be mislead when taking such
measurements, e.g. move the probe over to ground on the other side of the
sense resistor and observe the zero-volt signal... and ditto elsewhere).
Got the T shirt on this one- all measurements are relative, using stored
values and the same probe with the same reference ground for the probe, also
using 100MHz DSO to capture as much as possible.
I have had problems with this part and failures, so in this design I have
implimented the 1R series resistor from mid point to BHS and a UF4003 from
this point to BLO as noted in a Harris aps note
 
L

legg

Jan 1, 1970
0
I think I am getting to the problem- not quite where I thought it was,
the bridge is a phase shift type, with 0V in both bridges have a common mode
switching frequency, and switch together, +v one bridge duty cycle
increases, the other decreases,-v the opposite.
By removing the load and applying a DC offset it appears that the pulse is
comming from the oposite bridge half, and appears to be from the half under
measurement when at 0V or small signal input.

Whoa. You are driving a common-mode choke with a phase-modulated H
bridge? The common mode fundamental output component of a phase
modulator is extremely large.

Are you sure you are not driving your sources and drains above and
below their power rails? Is current really zero before the second
conduction event?

RL
 
T

Terry Given

Jan 1, 1970
0
Anthony said:
Its definately secondary turn on, albiet maybe smaller than I first thought
the above is not realy practical as its not a smps, its a discreet modulator
driving the HIP for an audio amplifier and the sense resistor is part of the
I limit system.
regards

OK, just a thought. But if you post that piece of the schematic, I'll
show you how to re-route the gate current and still keep the current
limit etc working.

Cheers
Terry
 
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