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Second Stage of Op-Am (Current to Voltage)

Discussion in 'Electronic Basics' started by Monty Hall, Dec 26, 2004.

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  1. Monty Hall

    Monty Hall Guest

    I'm reading Tom Frederickson's "Intuitive IC Op Amps" - in particular pg 15
    concerning the op-amp schematic, and am not sure how the second stage of the
    op amp works. This stage that takes the single ended current and converts
    it a voltage before it's off to the output stage.

    The current input goes to the base of a transistor whose emitter is
    connected directly to ground and the freq compensating capacitor is placed
    across the collector and base. How does this configuration work -
    especially if the base input current is negative? Current is sourced from

    Horowitz and Hill's 741 schematic has a 300 ohm resistor on the base input.
    Is this where the current to voltage conversion takes place and was omitted
    by Frederickson? In either case, still not sure where current comes from
    when current mirror sinks current in stage 1.

    If the sinking current mirror pulls from the cap, I would expect the mirror,
    when sourcing current, to load the cap by symmetry. But in a sourcing
    configuation, the transistor is now forward biased. Can somebody explain how
    current is converted to voltage in stage 2?

    Totally unrelated, but what does it mean when a NPN transistor has two or
    more emitters in a schematic?


  2. Active8

    Active8 Guest

    No. You should draw this out for us.

    created by Andy´s ASCII-Circuit v1.22.310103 Beta

    But I'm sure the 2nd stage base is maintained 1 Vbe above ground
    (unless you meant that the emitter goes to Vee. Maybe you mean this:

    | |
    | |
    |< >|
    -| |-
    |\ /|
    | |
    | | |
    | | Vbe |/
    Vbe +-----+ +------------|
    | | | |>
    | | | |
    \| | |/ |
    |---+----| |
    <| |> |
    | | |
    | | |
    | | |
    created by Andy´s ASCII-Circuit v1.22.310103 Beta

    See, the mirror bjt's Vc can't go below ground.

    current limit.

    That it has two or more emitters in silicon. Also shorthand for
    parallel devices sometimes.
  3. Monty Hall

    Monty Hall Guest

    I have a question about stage 2 of a 741 op-amp - the current to voltage
    converter. The schematic of the 741 in following link is similar to
    Horowitz and Hill and Intuitive IC Op-Amps. I didn't mention I was speaking
    of the 741 in my first post.

    Just curious what happens when I have a negative current(Iout) from the
    current mirror in stage 1 (between collectors Q4 & Q6) going into stage 2.
    I don't see how the circuit can deliver current TO the mirror except through
    the capacitor. I would expect the output voltage from stage 2(Q17
    collector) to be constant - not an unbounded voltage ramp due to the cap for
    a negative Iout.

    If I applied inputs w/ a very small difference in voltage in an op loop
    configuration, can I theoretically get a non saturated output voltage(I
    thought you could)? How do you compute Q17 collector voltage as a function
    of input current Iout or the input voltage delta?

    Is the assumption that Iout = A(Vnon-inv - Vinv) where -Ibias < Iout < Ibias


  4. Jamie

    Jamie Guest

    the collector most likely is connected to a feed that is supplying + volts.
    current in the base/emitter of the transistor will govern how much
    pull down the + feed to the collector will get.
    thus the effect is you have a current that is controlling the
    conductance of the transistor which is pulling the + down to the
    ground point which then gives you a voltage shift effect.
    with out looking at a print that is the best i can come up with.
  5. Active8

    Active8 Guest

    Again, how can the collector of Q6 drop below the negative supply
    and therefore sink current?? That node is pinned at I_Q13b*100 +
  6. Monty Hall

    Monty Hall Guest

    In an op-amp, doesn't the differential amplifier(consisting of bias current,
    differential transitor pair, and current mirror)transduce the difference in
    input voltage to a current? From the schematic it looks as if this line,
    call it Iout, is the line going to the right into Q16 @ the point where Q4 &
    Q6's collectors connect.

    I've read that this current is Iout = I_Q1e - I_Q2e where Q1 & Q2 current
    is conserved against a bias current. The possibility of Iout being negative
    is possible (-Ibias/2 < Iout < Ibias/2). Where does Iout go such that it's
    converted into a voltage @ Q17's collector? Or is Iout = I_Q1e - I_Q2e = A
    (Vnon-inv - Vinv) & (-Ibias/2 < Iout < Ibias/2) incorrect?


  7. Active8

    Active8 Guest

    Yeah, the difference between the current from the mirror and the
    current thru Q2. You'll get a little voltage wiggle, too.
    Throw that book away. It's obviously I_Q4c - I_Q6c
    Doesn't exist. I told you before. That Iout node is at I_Q17 * 100 +
    2 * Vbe volts above the negative rail. If you *do* drive that node
    below that the Miller stage bjts will cut off and then there's no
    current through the bjts to set the Vbe's or the drop across the 100
    emitter R of Q17. Your output will clip.
    Where do you get that? It's vague and it doesn't even make sense.
    Cave men communicated better with colored stones.
    It doesn't really matter at this point. It's also a voltage signal
    that controls Q17 which is loaded with a current source which gives
    a big voltage swing.
  8. Monty Hall

    Monty Hall Guest

    From the schematic below, can Iout be bidirectional? Included is the
    schematic of Fredericken's(Intuitive IC Op Amps) basic op-amp sans stage 3 -
    emitter follower unity gain output. How is Iout converted to voltage?

    In Frederickson's text:
    "The second stage of the basic op-amp converts this current back into a
    voltage Vout, that will become the output voltage of the op amp. An
    internal capacitor, Cc, is the component that does this conversion of
    current to voltage."

    It would seem that this statement has answered my question. How is Vo
    calculated and how can Iout be negative? Active8, I'm speaking wrt
    Frederickson's text & schematic below. He clearly states Iout can be

    First I want to make sure about the bi-directionality of Iout - it seems
    there is disagreement here from other posts. How would you characterize
    stage 1's output @ Vo'. Is it:
    1.) a current pump w/ Iout(V+ - V-) = Ic2 - Ic1 & 2Ic < Iout < 2Ic
    2) a high impedance voltage source Vo' = Av(V+ - V-)
    3) something else

    If it is 2, I would appreciate it if you can answer the following:

    1. How do you compute Vo'? IOW, how is the transfer function of Vo'/(V+ -
    V-) & Vo/(V+ - V-) derived? Basically not sure how calculate collector
    voltage that has an active load. I've always assumed that the delta in
    collector currents from Q2 and Q4 make a current pump @ that point.

    2. Why is the discussion about Iout = Ic2 - Ic1 relevant if 2 is true? Ga
    Tech/Penn State/MTU/UNLV/... lectures always have DC analysis of the
    differential amplifier active load end w/ Iout(V+ - V-) = Ic2 - Ic1 and stop
    short of stage 2 conversion of current to voltage. However, Frederickson's
    "Intuitive IC op-amps" mentions the cap is where the conversion takes place.
    Other - specifically Active8 - may choose "3) something else" because he
    believes that Iout can't be negative.



    +Vcc +Vcc
    o o
    | |
    | |
    2 Ic = Bias Current Io = Bias Current
    | |
    | |
    | |
    o------o-----o |
    | | |
    |< >| o-------o----o Vo
    Vin(-) -| Q1 Q2 |- Vin(+) | |
    |\ /| Cc --- o
    |Ic1 Ic2 | --- |
    | | Vo' | |/
    | o----------------------o---o-|
    | | Iout = Ic2 - Ic1 (+/- 2 Ic)|>
    | | o
    | | |
    | | Ic1 |
    | o |
    | |/ |
    o----o---o-| Q4 |
    | | |> |
    | | Ic1 o |
    | o | |
    | |/ | |
    |--| Q3 | |
    |> | |
    | | |
    -------o |
    | |
    | |
    -Vee -Vee
    (created by AACircuit v1.28.4 beta 13/12/04
  9. Yes. Iout is the difference between Ic2 (designated as leaving Q2-C)
    and Ic1 (designated as entering Q4-C). Since both are positive and
    about matched, their difference can take either sign.
    You can think of Cc and that (nameless) rightmost transistor
    as an integrator (if Early voltage is infinite) or as a high-gain
    stage with a very low frequency pole (otherwise).
    That seems to eliminate the role of that nameless transistor.
    Since it functions to hold its base at nearly constant voltage,
    by driving the top end of Cc, that is quite an omission.
    Anybody who disagrees with the bi-directionality is mistaken.
    Ok. We usually call that a current source.
    In the simplest model of that circuit, you need not compute it
    at all. Qnameless holds it constant by virtue of it low input
    impedance relative to the output impedance of Q2-Q4.
    Then stop worrying about the voltage transfer function.
    Write the transconductance transfer function. With very
    little error (easily accommodated as a 2nd order effect),
    you can use simple device transconductance to derive it.
    Not going there.
    If he truly believes or stated that, throw out his book. It will
    do more harm than good with respect to your understanding.
    Are you sure you are not mischaracterizing him?
  10. Monty Hall

    Monty Hall Guest

    Larry thanks for the response!!!! It's exactly what I was looking for! The
    discussion in another subthread w/ Active8 threw me for a loop - as he
    didn't believe a negative Iout could exist. Finally, I can ask my real

    If the cap is a current integrator that does the transduction to voltage,
    wouldn't the output ramp wrt time until saturated in an open loop
    configuration & (V+ - V-) < 0? Of course, integration would stop when (V+ -
    V-) == 0 because Iout ==0. The (V+ - V-) < 0 can be substitued w/ > 0 ,
    just want Iout to be consistently non zero & + or - wrt time.

    It seems very contrary to some web pages & text that say that the op-amp can
    be operated open loop and the output is as simple as Vout = A(V+ - V-). If
    current integration is true - any (V+ - V-) < 0 would cause saturation -
    eventually - due to Iout != 0 - right? If this is not the case and the
    op-amp output voltage settles to a value in an open loop & (V+ - V-) < 0
    configuration, why does the settling happen despite Iout != 0?

    Larry, sorry if my terminology in my prev post is unclear - I'm a newbie to
    EE :) All others, the schematic of op-amp stage 1 & 2 @ bottom of page.


  11. Active8

    Active8 Guest

    That's what Monty was saying, but in his previous posts, he was
    refering to another drawing and here he's got the component refs all
    screwed around compared to that one of many of the differing 741
    schems available that he linked to. At least we have a ref now.
    You guys are assuming that the active load perfectly mirrors the
    current in diff branches aren't you?

    I used to believe that the current would flow bidirectionally 'till
    I wondered where I'd get that reverse current. You both are welcome
    to simulate this circuit in Spice and try for yourselves.

    I pulled out an old NPN diff stage so my circuit's upside down. Same
    Cc is a pole. Nothing more. I've got no Miller stage at all and I
    can get a voltage across a resistor which is the same thing you get
    if you replace the active loads with resistors.
    The Miller stage bjt is for voltage gain. I'm repeating myself often

    Show me.
    Show me.
    Av = 40Ic_Q2(Ro_Q2 || Ro_Q4 || Ri_Qmiller) something like that. 1st
    order quess.

    Because there's nowhere to get it from!
    I didn't write the POS.
  12. Active8

    Active8 Guest

    Told you what you wanted to hear. You need to hang with Paul
  13. Monty Hall

    Monty Hall Guest

    Virtually all 741 op-amp schematics that I've seen are differential
    amplifiers with current mirror active load. Not sure why you need to be so
    specific for general theory of operation. Is there a 741 that deviates
    significantly from this? I wasn't expecting your response to be different
    that your other posts. The components are not screwed around for fresh eyes
    to my question.
    Can't speak for Larry, but I am and so are several texts and lectures.

    I was looking to understand the op-amp analytically - not plug and chug root
    finding in SPICE. I want an articulation
    as to why it works - not "it just does" or "what else could it be...",
    "where else could it come from" - heard those a million times. Simply
    put... please prove it - analytically. So far it doesn't seem you're
    defending your position very well - or rather at all. That's why you're
    "repeating" yourself. "SPICE says Iout can't be negative" fine - then
    please explain/prove why (analytically using dc-analysis or small signal
    analysis) or point me to some text that can.

    Please refer to "Intuitive IC Op Amps" on page 14.
  14. Monty Hall wrote:

    I haven't been following the details of this thread very well, so I
    hope this is useful. Have you read through the National semiconductor
    opamp tutorial, yet?

    It goes through a generic but simplified opamp, pretty thoroughly.
  15. I believe that Iout can't be negative in the steady state because there
    isn't a source of current other than leakage through the output
    transistor. Current in the positive direction will flow through the
    diode in the output transistor.

    However, the current never has to go negative to control the output. It
    simply has to control the positive Iout appropriately (which in turn
    controls Vbe, in a way that depends on beta), and work that against Io.
    The output can vary between -Vee + Vbe and Vcc simply by controlling the
    base current.

    Robert Monsen

    "Your Highness, I have no need of this hypothesis."
    - Pierre Laplace (1749-1827), to Napoleon,
    on why his works on celestial mechanics make no mention of God.
  16. There is some input for which the output is at mid-rail. There is a
    small range of inputs near that point for which the limited DC gain
    the circuit has allows the output to not be saturated in the steady
    state. For any input outside that small range, the output saturates
    near the Vcc or Vee rail.
    Approximately true. True if you ignore the limited Beta of
    Qnameless and assumes its base current to zero.
    Not sure what you mean here.
    Typically, trying to operate an op-amp open loop does not
    work. For most applications, it is best thought of as an
    integrator where the feedback drives it to a non-saturated
    stable operating point.
    Yes, subject to the approximation of infinite Beta.
    That would be where you are analyzing for finite open-loop
    gain. That gain is somewhat unpredictable, and can vary
    widely in actual op-amps.
    You can learn terminology as you go.
  17. Well, if I was assuming that, I would have said that Ic1 and Ic2
    were matched rather than "about matched".
    It is obvious that either Q2 or Q4 can have the greater
    collector current. There's your reversal. Why should
    we need Spice to discern this?
    If you mean to contradict with a simulation, you will have
    to show your circuit, its input, and the observations that
    you claim are at odds with my conclusions.
    Cc is a feedback element in an inner loop here. In order
    to find where the excess phase shift of this circuit happens,
    it will be necessary to treat Cc as something more than
    just "a pole".
    It is worth noting that it also serves to keep the collector-base
    voltages of Q1 and Q2 at about the same values. This is
    important for input offset stability. Your circuit without the
    post-diffamp gain stage will suffer a funky step response
    due to thermal effects that this stage will not show.
    Whenever Vo slews upward faster than is needed to supply
    Qnameless base current, it is because Iout is flowing toward
    the diffamp.
    You seem to have ignored the additional gain that occurs
    thru the Q1,Q4 path. Perhaps you do not understand the
    role of the Q3,Q4 current mirror here. If you did, then
    the Iout bi-polarity would not be in controversy.
    What about Q4? Do you think it is in cutoff when Vo
    is mid-rail?

  18. Active8

    Active8 Guest

    Because you were blabbering about Q1, Ic1, with no circuit to refer
    to. Notice I correctly guessed the circuit, not the reference
    They're not, but they don't get really wierd 'til you push the
    I told you Iout can't be negative before I pulled that circuit.
    Don't be an ass. You'd probably save time and frustration if you
    *did* take the time to do this in Spice. It's much easier to see the
    currents and why they're not what you expected.
    I told you. The circuit can never do this. Vo' is pinned at 1 Vbe
    above Vee. If you drove Vin(+) so high that it cuts off, Q4 will try
    to get that current from the next stage and it can't. Q4's collector
    will drop below the Vbe (head for the lower rail) of the 2nd stage
    and the 2nd stage will be in cutoff as a result. Replace the 2nd
    stage with a resistor connected to (Vcc - Vee)/2 or if you want that
    bidirectional behavior.

    Was that articulate enough?
    I don't have it and I suspect he's *not* talking about the same 741
    circuit. If he is, he can't see.
  19. Active8

    Active8 Guest

    I didn't. I first explained to Monty that you can't get a reversal
    of current in this circuit no matter how hard you try - you can't
    get a voltage at that Iout node that's lower than the voltage of the
    Miller stage emitter. There's no source.
    Which were wrong. Load the diff stage with a resistor connected to
    halfway between the rails and you *can* get that current reversal.
    WTF? Poles and zeros are *exctly* what you want to look at when
    determining phase shifts.
    That's an effect of Cc. Iout would never need to *draw* current in
    order to *supply* it. OP is talking about the diffamp demanding a
    current reversal and that can't happen in this circuit.

    You can not find any DC state in the circuit below where Iout
    reverses. Post the voltages where it happens.

    I just love the way you guys are talking poles and integrators when
    you haven't even established the DC bias point.
    No I haven't. See the Q4 impedance term in || with the other loads?
    You can't even seem to determine zero input bias point voltages it
    all one needs to do to show that bidirectionality can't occur here.
    ROFLMAO. When Vo is mid-rail, currnt flows to the right from the Vo'
    node. So even if Q4 was in cutoff (and it isn't), it wouldn't
    matter. The current would come from Q2.
  20. So, you believe that Q4 cannot conduct at a lower
    Vce than that? How do you think saturated BJT's work?
    You can get it with the circuit as Monty drew it.
    I see no contradiction here beyond bare assertion.
    If the Qnameless/Cc combo provided only a single pole,
    calling "a pole, nothing more" would be fine, I guess. My
    point is simply that it has more effect in applications where
    closed loop stability becomes an issue.

    Consider this point carefully when asserting that I was unable
    to discern the DC operating point.
    I do and did see it. It is a minor term.
    You would not be able to state such a non-fact if you
    had understood my point about thermal response. To
    get there, I had to know the approximate DC biasing.
    In that state, Q2 and Q4 collector currents are nearling balanced.
    To say the output comes from one only is oversimplified. Once
    at that state, if Vo begins to move positive at a rate faster
    than Ib(Qnameless)/Cc, net current at Vo' will be leaving
    to the left. According to your way of thinking, it would be
    going to Q4.
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