SDRAM

[RobertP]

Does someone know if there is a way to force SDRAM chip data outputs
into High-Z state asynchronously? Is asserting CS inactive sufficient?

 

[Stefan Heinzmann]

Does someone know if there is a way to force SDRAM chip data outputs
into High-Z state asynchronously? Is asserting CS inactive sufficient?

No (unless I've misinterpreted the JEDEC standard). The only
asynchronous input is CKE, and deasserting CKE alone won't do what you
want. You may want to have a look at the relevant standards at www.jedec.org

 

[Arie de Muynck]

Does someone know if there is a way to force SDRAM chip data outputs
into High-Z state asynchronously? Is asserting CS inactive sufficient?

No.

We had problems when a CPU watchdog fired in the middle of a burst
transfer - the DRAM outputs stayed active and the Boot Flash could not be
read anymore.
The problem was solved with some glue logic in a CPLD that gave off an abort
cycle to the SDRAM when the reset did tri-state the micro's outputs.

Regards,
Arie de Muynck