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sdram --> ddr design possible?

Discussion in 'Electronic Design' started by Dan Kuechle, Feb 4, 2004.

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  1. Dan Kuechle

    Dan Kuechle Guest

    I currently have a (single data rate) sdram design that runs at 40mhz.
    Sdram is used primarily for low cost, not for speed. We want to switch over
    to DDR (double data rate) because prices are getting cheaper than sdr sdram
    and densities are getting higher. If anything, we would want to go to a
    wider bus at 20mhz, rather than run at higher frequencies. From what I can
    see about DDR, this would not be possible as there is a minimum frequency of
    about 80mhz according to the spec sheets. Could someone in the "know"
    verify this: that ddr sdram needs its clock to be within a fairly narrow
    range... greater than 80mhz and less than its max clk speed. Any way around
    this?

    Thanks

    Dan
     
  2. Clock phasing in DDR is rather important, so they use a DLL or PLL
    inside the SDRAM chip. This leads to the lower frequency limit.

    Various chips may have test modes in which the DLL or PLL is disabled,
    but I'm not sure if this will work the same in chips from different
    manufacturers, and I don't think the I/O timing will be guaranteed in
    this mode.

    80MHz (not mHz!) isn't terribly fast. Why can't you run your
    controller at 80MHz? This should be cheaper and easier than using a
    bus that's four times as wide at 20MHz.

    My latest DDR SDRAM interface in an FPGA clocks at 160MHz (data rates
    of 320Mbps per pin) and uses a 64 bit bus.
    80MHz sounds ... pretty close to DC to me.

    Regards,
    Allan.
     
  3. Oops. Can't count. That should be a 32 bit bus connecting to two 16
    bit wide chips.

    Regards,
    Allan.
     
  4. You may want to read the JEDEC standard document JESD79C
    (www.jedec.org). It defines the common ground you can expect from DDR chips.
     
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