dlharmon said:
The ADC will be running continuously with the data being stored to
SDRAM (circular buffer). The problem with software triggering is the
aliasing of signals over 40MHz. I plan to use equivalent time
sampling. I should have noted that in the original post. I need the
trigger data so I can know where to put each data point on the screen,
and 12.5ns is not precise enough. For instance, what I need to know is
that the trigger occurred 3.4ns before the 12345678th clock cycle of
the ADC. This is one of those problems I see no digital solution to.
I realize the limitations of undersampling/equivalent time sampling,
and most of them will not matter for this particular application.
Tek has some info on equivalent time sampling here:
http://www.tek.com/Measurement/App_Notes/RTvET/ap-RTvET.html
I will be publishing this design on my website once it is built and
working.
Thanks
Darrell Harmon
http://dlharmon.com/sbc.html
Equivalent time sampling can be extraordinarily difficult and here are
some of the reasons why.
Your trigger system bandwidth has to be as high as the equivalent time
frequency response.
You have many more sources of error and jitter. Individual components
must be a LOT better than the equivalent time resolution multiple to
stay within the total very much smaller error budget.
Your trigger threshold has to be absolutely independent of the input
waveform. Small cycle-cycle variations in the input waveform can cause
catastrophic shifts in the effective trigger threshold even when those
changes happen far outside the area of interest. This is common when
looking at digital signals. Fixing this is harder than it sounds.
So, now that you have your trigger jitter plus A/D timing jitter down to
some fraction of the equivalent time clock interval and it's all
independent of input signal level and waveform, you're ready to build
the interpolator. Oh, don't forget that the aperture time of your A/D
has to be compatible with the equivalent time sampling interval.
Otherwise you'll have excellent time resoluton on a smeared out version
of the actual input.
In the TEK TDS540, they do it this way.
At the trigger event, start two fast positive ramps and store the
acquisition memory reference pointer.
At the next positive clock, start discharging the first ramp at a slower
rate and time how long it takes to discharge.
At the next negative clock, start discharging the second ramp at a
slower rate and time how long it takes to discharge.
This eliminates all the problems you get when the clock and the trigger
are almost coincident. You always have at least one good ramp interval.
But you need two of everything. And you need an absolutely symmetrical
clock.
Remember that if you're not saving all the samples, you also have to
remember the time since the last saved sample to do the interpolation.
I can't give you any more info on how they do it 'cause it all
disappears inside a massive custom IC.
You also have to manage the acquisition memory. You have to sample
continuously until you get the trigger, then continue to fill the
post-trigger memory. Then save the interpolation value. Then map into
a different memory space to start the pretrigger acquisition for the
next run. At some point, you have to retrieve all this info and map the
multiple acquisition memory spaces into the display space properly
interleaved. If you're not in a hurry and don't need to scroll the
screen and don't need the info later, you can use one memory and
transfer to the screen after each acquisition cycle.
Judging from the cal procedure, there's a huge amount of internal
calibration and firmware to make all this interleave properly.
If you go back 40 years and look at some sampling oscilloscope
schematics, you'll find a different scheme.
Start with two matched current sources, one positive, one negative.
Discharge your holding cap to ground.
Start the positive current on the trigger signal.
Start the negative current on the next clock edge.
Turn off both sources before the mismatch causes the cap voltage to
drift. The volts on the cap is a function of the relative timing of the
trigger and clock. Sounds simple, but doing all that switching without
introducing errors is a real trick.
I once implemented a crude version of this with a GAL20V8. Use the
output tristate control. Tie resistors from two outputs to a cap.
Turn on both outputs...the voltage divider holds the cap at vcc/2.
Tristate one output on the trigger and the second one at the next
clock. Voltage on the cap is a measure of the difference.
It's not a linear ramp, but the shape is known. Works better than I'd
expected. Sounds like redundant functionality, but when your trigger
rate approaches the clock interval, it can be useful to sense clocks
that happen before the trigger and just throw away the ones where
the clock is way too early. The early sampling scopes used a sort of
PLL/FLL that predicted where the next trigger would be. Not so
important if you have
digital memory.
The project died because I couldn't come up with a cheap sample/hold
to put ahead of the PIC A/D...and a TDS540 fell into my lap.
Happy sampling,
mike
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