Schematic preferences

[D Yuniskis]

Hi,

Of course, this is *highly* subjective -- but, I'd enjoy hearing
folks' "conventions" used when preparing schematics (that *others*
will consume -- how you scribble for your own purposes isn't
important as it depends a lot on what *you* want out of the
drawing).

I try to follow some general rules -- but also feel free to bend
them as needed. Most have evolved over the years from different
employers, standards, experience, etc.

E.g., I *tend* to prefer landscape orientation -- though I
drew a B size "portrait" this morning in lieu of a C size
landscape.

I try to include a block diagram of any "sizable" design early
in the document. I try to draft the individual pages so that
they roughly correspond with the blocks in that diagram.

I prefer spreading things over one sheet instead of trying to cram
everything onto one sheet -- unless the design is small enough
to do so without making that sheet cluttered. I.e., it is easier
to trace a signal on a single sheet than to have to flip to
another sheet; but, if there is a ratsnest of signals on that
one sheet, then tracing the signal can be perilous.

Smallest page size to realistically support the design subject
to the remainder of these criteria. E.g., sure, you can fit
everything on an E-size drawing, but reproducing that drawing
(either full size or in "published" documentation) and *using*
that drawing become a real PITA!

[I vacillate between preferring B or C size drawings. C is nice
in that it reduces to A nicely (i.e., with the same aspect ratio)
OTOH, B is nice because reducing to A leaves room along the
binding edge -- which must be located "above" the drawing! -- for
three hole punch *or* more professional binding. And, B size
can always be reproduced full size with "fold outs". (frown) B
size (reduced or otherwise) is currently en vogue -- perhaps a
consequence of my aging eyes? :> ]

Aside from "general power", all signals that span pages *must*
come to the edge of the page. I don't like hunting for signals
in the middle of a page even if there is a grid reference to help
me locate it. It's just easier to conceptualize: "OK, this is
used elsewhere" or "This comes from someplace else" so I
know when something I am interested in involves other sheets.

One signal, one name. One *instance* of that name per sheet!
Signals spanning pages are named at the edge of the page.

For designs of "suitable complexity" (in terms of sheets/signals),
I tag off page references with locations of the other "end(s)"
of the signal. If its a small design -- or, if the schematic is
broken down intuitively -- I assume the "other ends" will be
self explanatory.

"Left to right, top to bottom"

Eschew buses -- except on "block diagrams". Show individual
signals. Avoid unnecessary "bends" in signals. *Most* signals
parallel to page edges (some tools prevent you from doing otherwise).

Symbols oriented horizontally and suggestive of the direction
of signal flow (i.e., a gate in a feedback path can point to the
left). "Rocket ships crash (and burn)" :>

Exploit symmetry and repetition. Step and repeat is your friend.

As with *anything*, color has no significance!

Avoid 4-way streets -- unless their use significantly cleans
up the appearance. "Dots" (big ones!) on all connections
(mandated by the relaxed 4WS rule).

Descriptive symbols (e.g., a diode bridge looks like a diamond)
and informative symbols (e.g., IEEE unless the device *really*
is a "black box" -- I don't consider *memory* to be a black box!)
DeMorgan equivalents as appropriate. (I won't get into the rules
I use for building symbols as they get pretty involved)

Reference designator before device name/value. Either both to
one side (left/right/top/bottom) or one on each side (left/right,
top/bottom).

Unless a connector(s) inherently *merits* location on a separate
sheet (e.g., a PCI connector whose "pins" feed many other sheets),
locate the connector with the signals that tie to it (i.e., no
sheets full of connectors).

Don't tie the schematic to a physical implementation. I.e.,
the symbol for a connector shouldn't physically look like
the connector just as the symbol for a transistor doesn't
look like the transistor itself! If you need to clarify
the appearance or pin layout of a component, do so in
text or other documentation outside of the "schematic" itself.

Decoupling caps specifically required by individual components
located proximal to the component symbols themselves. Other
"general" bypass caps grouped on a single sheet. Power and
ground connections not explicitly shown on components tabulated
on that same sheet, if possible.

Only *terse* notes re: layout/manufacture/test on the actual
drawings; anything more verbose goes on a "notes" sheet.

On analog portions of the design, test voltage annotations
and 'scope traces, where *essential*. Remember, everything you
put on the drawing has to be *maintained*! If you make a change,
are you prepared to capture another 'scope trace? :>

Document history on the cover page *only*. One firm I worked for
used to summarize *all* revisions of a schematic *on* the schematic.
I.e., lots of little "windows" showing portions of the schematic
as they existed previously. I think this is a poor man's way of
*not* using "proper" document retrieval systems (i.e., if I
need Rev C of a design, then I should fetch the Rev C documents!)

I suspect there are many more that I just take for granted and
have failed to mention, here. :< *Somewhere* I have a document
formalizing all of these things. Though I suspect it is in
a format particular to a DTP program that I no longer have
on-line! :-/

 

[Jon Kirwan]

Of course, this is *highly* subjective -- but, I'd enjoy hearing
folks' "conventions" used when preparing schematics (that *others*
will consume -- how you scribble for your own purposes isn't
important as it depends a lot on what *you* want out of the
drawing).
<snip>

I was trained at Tektronix for drafting electronics, so my
preferences come from there.

Aside from "general power", all signals that span pages *must*
come to the edge of the page. I don't like hunting for signals
in the middle of a page even if there is a grid reference to help
me locate it. It's just easier to conceptualize: "OK, this is
used elsewhere" or "This comes from someplace else" so I
know when something I am interested in involves other sheets.
<snip>

Let me state the following rules used at Tek:

(1) Unless clearly justifiable for other reasons, electron
flow from bottom of page upwards to the top. All parts
oriented so that this is obvious. (No BJT spun around to
make electron flow go otherwise, unless I can _justify_
clearly why it reads better.)

(2) Signals flow from left to right across the page.

I think of these two rules, easily. The electrons flow like
a waterfall upwards (or positive charges flow down, your
choice) in order to "permit" signals to flow across, from
left to right. The signals ride across the sheet on the
flow.

(3) Don't bus power around unless there is some physical
characteristic that must be emphasized by doing so. If the
emitter of a PNP BJT is tied to +5, I don't bus the emitter
over to some heavy black line tied to power. I just stub it
right there to the named +5 rail. It does NOT help
readability to have lots of black lines running all over the
place, almost as though they are signal lines. In fact, it
distracts from understanding. You don't need to know any of
the other connections to that named +5 rail to know what is
happening at the BJT. All you need to know is that it is at
that rail's potential. The wire just adds "noise" to the
page and makes you go trace around looking to see that it
actually _is_ a rail and not something else.

That's enough for now, I suppose.

Jon

 

[krw]

Hi,

Of course, this is *highly* subjective -- but, I'd enjoy hearing
folks' "conventions" used when preparing schematics (that *others*
will consume -- how you scribble for your own purposes isn't
important as it depends a lot on what *you* want out of the
drawing).

I really want the same thing out of the schematic as do my
"customers". In a year I won't remember what I did, so it's got to be
readable (source code is the same deal - in spades).

I try to follow some general rules -- but also feel free to bend
them as needed. Most have evolved over the years from different
employers, standards, experience, etc.

E.g., I *tend* to prefer landscape orientation -- though I
drew a B size "portrait" this morning in lieu of a C size
landscape.

Yes, Landscape always seems to work out better. I just use 11x17 and
stick it in a notebook sideways, with a fold. I'd do longer (I really
print with a 1" offset so it comes out 11"x18") but haven't found I
need more space that direction (without running out of vertical space
first). OTOH, the other engineer likes C-size prints. I find they're
a PITA on the bench (or pretty much anywhere). I end up printing his
on 11x17 and squinting. ;-)

I try to include a block diagram of any "sizable" design early
in the document. I try to draft the individual pages so that
they roughly correspond with the blocks in that diagram.

I try, though the drawing tools suck. I'd much prefer a hierarchical
design, killing both birds, but the software isn't up to it.

I prefer spreading things over one sheet instead of trying to cram
everything onto one sheet -- unless the design is small enough
to do so without making that sheet cluttered. I.e., it is easier
to trace a signal on a single sheet than to have to flip to
another sheet; but, if there is a ratsnest of signals on that
one sheet, then tracing the signal can be perilous.

I can usually keep off-sheet connectors to a minimum, placing an
entire "channel" or such one sheet - maybe two. There is usually a
logical break somewhere. It often costs a bit of paper, though.

Smallest page size to realistically support the design subject
to the remainder of these criteria. E.g., sure, you can fit
everything on an E-size drawing, but reproducing that drawing
(either full size or in "published" documentation) and *using*
that drawing become a real PITA!

Sooner or later the design is going to overflow a sheet. Not only is
"E-size" a PITA, but so is "C-Size", IMO. Larger pages have more
signals running around, too. Long wires are hard to follow.

[I vacillate between preferring B or C size drawings. C is nice
in that it reduces to A nicely (i.e., with the same aspect ratio)
OTOH, B is nice because reducing to A leaves room along the
binding edge -- which must be located "above" the drawing! -- for
three hole punch *or* more professional binding. And, B size
can always be reproduced full size with "fold outs". (frown) B
size (reduced or otherwise) is currently en vogue -- perhaps a
consequence of my aging eyes? :> ]

Get glasses. ;-) Bifocal reading glasses (two strengths, both for
close work) work for me.

Aside from "general power", all signals that span pages *must*
come to the edge of the page. I don't like hunting for signals
in the middle of a page even if there is a grid reference to help
me locate it. It's just easier to conceptualize: "OK, this is
used elsewhere" or "This comes from someplace else" so I
know when something I am interested in involves other sheets.

I agree, though I'd rather have signals connected on a page by name
(as long as it's *clear*) than connectors broken apart and scattered
all over the schematic. Sometimes it's not clear what the best
solution is.

One signal, one name. One *instance* of that name per sheet!
Signals spanning pages are named at the edge of the page.

Good idea, when it's possible without making the sheet look like a
rat's nest. It usually is, though there are exceptions.

For designs of "suitable complexity" (in terms of sheets/signals),
I tag off page references with locations of the other "end(s)"
of the signal. If its a small design -- or, if the schematic is
broken down intuitively -- I assume the "other ends" will be
self explanatory.

*ALWAYS* include off-sheet references.

"Left to right, top to bottom"

Left to right (bidirectionals go either way unless there is tristate
output on the net - then it gets more complicated). Top and bottom
are for power only.

Eschew buses -- except on "block diagrams". Show individual
signals. Avoid unnecessary "bends" in signals. *Most* signals
parallel to page edges (some tools prevent you from doing otherwise).

Wrong! Busses wherever they make sense. *NEVER* connect bussed
signals off page. Off-page connectors on busses are shown as busses
*only*. They get fanned out to nets on the page, as close to the part
as possible. Do you really draw 64 individual wires with 64 off-page
connectors for each wire in a 64-bit data bus? Ick!

Symbols oriented horizontally and suggestive of the direction
of signal flow (i.e., a gate in a feedback path can point to the
left). "Rocket ships crash (and burn)" :>
Agreed.

Exploit symmetry and repetition. Step and repeat is your friend.

Hierarchy is your friend. Schematic entry tools aren't. ;-)

Be careful with step and repeat. It's *really* easy to forget to
change all instances of facilities that differ between copies. DRC
and browsing the netlist can help here.

As with *anything*, color has no significance!

Significance, no, but importance, yes. IOW, the netlister shouldn't
care about color but the human reading it does. It *must* be
consistent.

Avoid 4-way streets -- unless their use significantly cleans
up the appearance. "Dots" (big ones!) on all connections
(mandated by the relaxed 4WS rule).

I don't have problems with 4-way streets. Dots are plain enough to
see.

Descriptive symbols (e.g., a diode bridge looks like a diamond)
and informative symbols (e.g., IEEE unless the device *really*
is a "black box" -- I don't consider *memory* to be a black box!)

IEEE symbols suck. Rockets and bullets, everything else is a box;
clocks and active levels marked appropriately

DeMorgan equivalents as appropriate. (I won't get into the rules
I use for building symbols as they get pretty involved)

Yes, and signal names must match the symbol's polarity.

Reference designator before device name/value. Either both to
one side (left/right/top/bottom) or one on each side (left/right,
top/bottom).

I put the RefID on top of the value with the value inside the
component if it fits.

Unless a connector(s) inherently *merits* location on a separate
sheet (e.g., a PCI connector whose "pins" feed many other sheets),
locate the connector with the signals that tie to it (i.e., no
sheets full of connectors).

That depends. Sometimes a connector sheet can be used to show the
layout of the connectors. This is very handy when there are a lot of
the same kinds of connectors. Again, the idea is to convey as much
information as possible about the board.

Don't tie the schematic to a physical implementation. I.e.,
the symbol for a connector shouldn't physically look like
the connector just as the symbol for a transistor doesn't
look like the transistor itself! If you need to clarify
the appearance or pin layout of a component, do so in
text or other documentation outside of the "schematic" itself.

Diagree. It's very handy to have our XLR connectors look like XLR
connectors, in the proper orientation. Information. Interboard
connectors and headers also are drawn physically (in order, odds on
one side and evens on the other). BNCs are drawn big-circle little
circle/dot (dots=male, circles=female).

Decoupling caps specifically required by individual components
located proximal to the component symbols themselves. Other
"general" bypass caps grouped on a single sheet. Power and
ground connections not explicitly shown on components tabulated
on that same sheet, if possible.

If possible. Large components get their own power/ground/decoupling
(sometimes clocks or references) sheets. Small components (gates,
op-amps, etc.) get power on the pages they appear. I'd change that if
I were king, but the software sucks.

Only *terse* notes re: layout/manufacture/test on the actual
drawings; anything more verbose goes on a "notes" sheet.

We put ECO notes on the sheets in red before the ECO and in blue for
one revision after, in addition to the "Notes:" block on page-1. We
also put a note on each subcircuit explaining what it is:

+--------------------+ +-------------------------------+
| 4-pole Butterworth | - or - | Load Switching Bus |
| H.P. F0=1kHz G=6dB | +---+---+---+---+---+---+---+---+
+--------------------+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
|8nF|4nF|2nF|1nF|800|400|200|100|
+---+---+---+---+---+---+---+---+

On analog portions of the design, test voltage annotations
and 'scope traces, where *essential*. Remember, everything you
put on the drawing has to be *maintained*! If you make a change,
are you prepared to capture another 'scope trace? :>

No pictures. They take way too much space. Voltages, yes. Keping
any documentation up to date is a problem. Notes are no different
than comments in code.

Document history on the cover page *only*. One firm I worked for
used to summarize *all* revisions of a schematic *on* the schematic.
I.e., lots of little "windows" showing portions of the schematic
as they existed previously. I think this is a poor man's way of
*not* using "proper" document retrieval systems (i.e., if I
need Rev C of a design, then I should fetch the Rev C documents!)

Disagree, sorta. We put the revisions on the first page of the
schematic and keep two or three (whatever fits). It's there as a
reminder only and certainly doesn't supercede the ECO system. We also
add notes to the schematic (in red) to incorporate if we ever hit the
board again. Again, those are reminders only and don't supercede the
problem reports and such.

I suspect there are many more that I just take for granted and
have failed to mention, here. :< *Somewhere* I have a document
formalizing all of these things. Though I suspect it is in
a format particular to a DTP program that I no longer have
on-line! :-/

Here's one. ;-) We have schematics that are essentially twelve itsy
pages of schematics crammed onto one C-sized page. *Very* bad, though
when I gagged during the interview it made big points with the
engineering manager. ;-)

 

[Tim Williams]

PNP emitters up, NPN emitters down!

Ah, but Tek doesn't do that -- IIRC (and maybe I don't), they often drew
balanced circuits symmetrically, like so;
http://webpages.charter.net/dawill/Images/Deflection Amp.gif

The side-by-side approach is more common outside of oscilloscopes, but does
lead to messier drawings because you're showing everything twice:
http://webpages.charter.net/dawill/Images/Tube Oscilloscope Vertical.gif
That, and the sheer number of passives indicated, is why this simple
balanced amplifier is 1133 pixels wide.

Tim

 

[Tim Williams]

I have one of those, actually.
http://webpages.charter.net/dawill/tmoranwms/Elec_Circuit_Rules.html
A bit dryer than conversation here, but gets the jist across. Motivation
being I wrote my own cheapass's component library, so I might as well add
something about its use.

Tim

 

[krw]

PNP emitters up, NPN emitters down!

That comes from +V on top, -V on the bottom.

Op-amp: (-) on top of (+).
D-FF: 'D' above 'Ck' (preset above D, Clear below Ck). Q above /Q

 

[krw]

When was the last time you saw a drafting droid? ;-)

Resolving that ambiguity by breaking that "intersection" into two tees
disappears the problem.

It takes valuable "routing" space. Signals should have as few bends
as possible across the page. This gets important if all sheet inputs
are on the left and outputs on the right.

 

[krw]

Hi,

Of course, this is *highly* subjective -- but, I'd enjoy hearing
folks' "conventions" used when preparing schematics (that *others*
will consume -- how you scribble for your own purposes isn't
important as it depends a lot on what *you* want out of the
drawing).

<snipped stuff already answered>

Let me add net-naming conventions to the discussion:

All voltages (nothing else) get a '+' or '-' prefix.

Negative active digital signals start with '/' or end in "_n" (leading
"/netname" gets converted to "netname_n" in an FPGA)

Differential pairs get a '+' or '-' suffix (so they collate properly).

I like BiCapitalization for words, and Under_Scores to note hierarchy.
e.g. ChanA_OutputGain. This also allows netlists to be collated
properly.

Hmm, dinnertime.

 

[krw]

You might find that your printer supports so-called Super-B-sized paper at
13"x19"... it's a worthwhile step up from 11"x17", IMO.

It supports 24" x 1-roll. It's an HP DesignJet. ;-)

13" doesn't fit in a notebook.

One thing that hasn't been mentioned is the size of the stock library symbols
suppled with the schematic capture program: Even though most people end up
drawing their own symbols anyway, the size of the supplied symbols tends to
set a precedent for the relative scale of various symbols. In my experience,
ORCAD goes for relatively larger symbols -- an ORCAD D-sized sheet sheet often
prints out without too much squinting necessary at 13"x19", whereas in many
other schematic capture programs it'd be pretty much unusable.

Orcrap's symbols are *huge*. I draw my own.

Do you use the European convention of drawing resistors as rectangular boxes
then? Or you mean just on bigger items like ICs?

No, resistors are squiggles. Just the bigger items. When I first
started in IBM, everything was a box. A resistor looked exactly like
a capacitor, like an AND gate, and a DFF. Schematics had to be drawn
on chain printers. Didn't like it much. ;-)

Although you have to be careful that people don't mirror the symbol on you.
(With multi-pin connectors, sometimes the hook-ups are a lot cleaner if
you go ahead and mirror the symbol, so it's a subjective call if you should
make a rule that symbols drawn to resemble the physical part should never be
mirrored or not.)

Whether or not it's mirrored depends on which side of the connector
you're looking at. ;-) Point taken.

I put a small gap in the outer circle so that it doesn't appear as though
you're shorting the inner conductor to the shield.

Works for me. It still looks like what it is (perhaps without the
tangs).

I usually give power rails and ground different colors (e.g., +5V in red,
ground in green). This was prompted by early versions of Pulsonix that made
it *way* too easy to accidentally end up with an isolated sub-net (e.g., a net
between an IC pin and a resistor) that was connected-by-name to ground or a
power rail (long story, but suffice to say that in more recent versions it's
now almost impossible to do this accidentally), so it provided some immediate
visible feedback if you were shooting yourself in the foot in such a manner.
I liked the effect, though, and hence have kept doing it, adding now, e.g.,
purple to indicate 50ohm traces. (These are all just net attributes so it's
easy to change colors or display everything in all black again if someone
prefers.)

I just put global connectors on the pins, or as close as possible. A
global power pin might connect a dozen pins on a processor.

Do you use PADS for layout? If so, do you use a 3rd party tool such as
Prescience to pass design constriants between ORCAD and PADS?

I don't do layout. The layout guy uses Allegro. The other hardware
engineer uses Layout, when he does layout (only legacy products
anymore).

 

[Jon Kirwan]

PNP emitters up, NPN emitters down!

John

Yes. Maintain the flow direction uniformly. Some
exceptions, but it's a good rule.

Jon

 

[krw]

Ah, but Tek doesn't do that -- IIRC (and maybe I don't), they often drew
balanced circuits symmetrically, like so;
http://webpages.charter.net/dawill/Images/Deflection Amp.gif

The side-by-side approach is more common outside of oscilloscopes, but does
lead to messier drawings because you're showing everything twice:
http://webpages.charter.net/dawill/Images/Tube Oscilloscope Vertical.gif
That, and the sheer number of passives indicated, is why this simple
balanced amplifier is 1133 pixels wide.

I like diff-amps with the components side by side, mirrored left and
right. +V at the top, -V at the bottom.

 

[Jon Kirwan]

Just by way of example, here's a poorly laid out circuit:

http://www.swtpc.com/mholley/PopularElectronics/Nov1967/PE_Nov_1967_pg30.jpg

In my opinion. Find the +rail and ground lines and trace
them around the schematic. What's the point in the busing
everywhere? How much do those 'wires' interfere with
following function?

Now, if you are point-to-point wiring stuff you might lay out
things and then run the heavy wire around like that,
soldering to it along the way, I suppose. Maybe. But if you
are trying to follow the operation with understanding there
are better ways to draw it.

It's not the worst example around. But it addresses some of
the points. Emitters from different PNP's pointing
differently. Emitters from NPN and PNP pointing the same
way. Bus wires trapsing around all over the place almost
looking as though they might carry signal. Etc.

Jon

 

[krw]

I prefer xSignalName, but I don't have any gripes about / or _n -- it's more
important that whatever standard someone chooses, that everyone else who then
works on the schematic adopts the same standard.

....particularly in the same schematic.

I really don't like prefixes (other than power) because the signal
names don't collate properly. A net and its negative should sort
together, just as diff pairs should sort together.

 

[krw]

On Mon, 18 Jan 2010 18:39:06 -0800 (PST), MooseFET

All parts have the power pins shown. The + is usually on the
top. The exception is references and regulators where it is
on the left.

What about gates? All subcircuits get power pins? What about dual
op-amps?

I never crossed lines as a connection point. If two lines connect
to another line, they are offset.

Again, that uses a additional "wiring channel" on the sheet. Dots
work fine.

The triangle ground symbol means the circuit ground of the PCB.

We use the triangle for analog grounds. A triangle with an "F" for
"field" (isolated external) grounds.

The
three line symbol means the connection to the chassis. The one like
this:
!

Yes, and

|
---------
-----
-

is a digital grounds. I know, they analog and digital grounds
_should_ be the same. They will be soon. ;-)

Mounting holes are shown if they have electrical meaning.
Shields?

Notes go in the lower left corner of the sheet.

We put general notes where they fit and specific circuit notes
pointing to the device or circuit they're describing.

The reference of a part encodes the page it is on. R307 is on page 3

We do that, sorta. Identical channels are numbered R1xx, R2xx,...
Rnxx, no matter what page they're on. In one schematic four channels
are on pages 3-7, but are still labeled R1xx for channel 1.

I also like Larkin's reference numbering from side to side with the
schematic being back-annotated after layout. That really helps debug.

 

[krw]

All my engineers (excepting me!) CAD their own schematics. I still
draw with pencil on vellum and let The Brat enter them for me. But I
check them very, very hard.

Are you claiming to be the last drafting droid? ;-)

 

[Tim Williams]

Busing isn't useless though. I like to draw equal signals across, like this
for instance:
http://webpages.charter.net/dawill/Images/RegBO.gif
The AC supply isn't the kind of thing you want wires hooked to globally, so
I would hesitate to assign named connections to it. It's a small circuit,
so it's not a big deal, and the buses stayed short. I could assign ground
to the output side, but decided against it. That would avoid the ugly drop
below the rectifier-filter, and maybe the IR LED connection could move
somewhere.

Other than that, I think my only complaint is this drawing doesn't have a
pleasing aspect ratio -- it's just too wide! The more primitive model isn't
as balanced, but it does have a pleasing ratio:
http://webpages.charter.net/dawill/Images/Regulated Blocking Oscillator.gif

This one is heavily bused:
http://webpages.charter.net/dawill/tmoranwms/Circuits_2008/Triangle.gif
I'm pretty sure I would draw it differently, but I may also retain the
buses. It doesn't seem right to label them seperately; the circuit is
closely connected, and yes, it is representative of the layout (which was
breadboarded).

One more example, a larger one:
http://webpages.charter.net/dawill/tmoranwms/Elec_Induction3.gif
For its size, I broke up the building blocks, putting lots of white space
between them. The components are fairly tightly spaced, as was my style at
the time. Signals weren't cleanly bused, like how R315 and 316 aren't in
line, that looks kind of weird. D308 is actually carrying a signal
backwards, but it's only a little ways, towards a common node, so it's not
too horrible. The supply lines are locally bused in some cases, and
floating in others (IC301 south, R314, etc.), which looks kind of sloppy,
maybe or maybe not worse than the alternative (studded with +V's just looks
too redundant).

Someone mentioned feedback paths can be reversed. Setting aside "I know
what you mean", would this control circuit be acceptable to mirror, just
because it's a feedback circuit? ;-) The obvious answer is, only if the
rest of the loop dominates the circuit.

Tim

 

[D Yuniskis]

Hi John,

On Mon, 18 Jan 2010 16:13:23 -0800, John Larkin


If one knows what's happening at that junction, that's fine, but it's
happened more than once that a drafting droid saw two lines crossing and
figured they should be connected.

Resolving that ambiguity by breaking that "intersection" into two tees
disappears the problem.

That's how I used to draw things. But, I found it often resulted
in clumsy signal routing -- just to avoid a 4WS.

I don't worry about people adding dots to *my* drawings. :>
The bigger worry I have is when schematics are reproduced
and it becomes difficult to determine if there is or isn't
a dot on the junction.

 

[D Yuniskis]

Yikes! Production would lynch us. After the layout is done, we
resequence the reference designators in physical and numeric order and
back-annotate the schematic.

Ditto. The problem I find with EDA tools is they don't let you
put "tags" in text on the sheets. E.g., if you have a note:
"D1 - D4 installed on heatsink" and you backannotate the
schematic, D1 may no longer be D1, etc. So, you have to manually
go through and update the notes. It would be nice if you could
set up cross reference tags like in DTP tools...

 

[Rich Webb]

Even more reason to offset, since that way a 4 way intersection can
_only_ be a crossover and if a wire butts up against another one it's a
connection, dot or not.

I think there's an ANSI standard that covers it, and probably an IEC one
as well, but offhand I don't know which one(s)

IIRC (my copy is at home) an appendix to AoE also makes this
recommendation. Of course, the Appeal to Authority isn't much of an
argument in and of itself.

It does sometimes look more "natural" to connect at crossings (e.g., the
canonical voltage divider, top to bottom, with a signal passing
"through" the junction left to right) but adding a small jog there is a
small price to pay for the avoidance of ambiguity. A "T" always
connects; a crossing never connects. And no humpies.

 

[Jon Kirwan]

Busing isn't useless though. I like to draw equal signals across, like this
for instance:
http://webpages.charter.net/dawill/Images/RegBO.gif

That is a _power_ supply. Sometimes, the signal _IS_ the
rail. However, that is still one I'd still draft somewhat
differently.

The AC supply isn't the kind of thing you want wires hooked to globally, so
I would hesitate to assign named connections to it.

I'm very much with you on that point.

It's a small circuit,
so it's not a big deal, and the buses stayed short. I could assign ground
to the output side, but decided against it. That would avoid the ugly drop
below the rectifier-filter,

It would probably help clarity.

and maybe the IR LED connection could move somewhere.

It does seem to need a change. The +rail tie is back a
little from where it means more (closer to the 2N3906 which
diverts its current) and not more to the left of the 470 ohm
resistor which really isn't as related to what is happening
there. Plus having both lines crossing over the ground rail
line like that...

Other than that, I think my only complaint is this drawing doesn't have a
pleasing aspect ratio -- it's just too wide! The more primitive model isn't
as balanced, but it does have a pleasing ratio:
http://webpages.charter.net/dawill/Images/Regulated Blocking Oscillator.gif

I don't think I would decide that a schematic is better or
worse on the X vs Y size of the plot. Okay, if it is 10
pixels high and 50,000 wide I might question something there.
But it's not something I worry as much about as keeping
signal flow moving left to right, electron flow bottom to
top.

This one is heavily bused:
http://webpages.charter.net/dawill/tmoranwms/Circuits_2008/Triangle.gif
I'm pretty sure I would draw it differently, but I may also retain the
buses. It doesn't seem right to label them seperately; the circuit is
closely connected, and yes, it is representative of the layout (which was
breadboarded).

I'd definitely draw that differently.

One more example, a larger one:
http://webpages.charter.net/dawill/tmoranwms/Elec_Induction3.gif
For its size, I broke up the building blocks, putting lots of white space
between them. The components are fairly tightly spaced, as was my style at
the time. Signals weren't cleanly bused, like how R315 and 316 aren't in
line, that looks kind of weird. D308 is actually carrying a signal
backwards, but it's only a little ways, towards a common node, so it's not
too horrible. The supply lines are locally bused in some cases, and
floating in others (IC301 south, R314, etc.), which looks kind of sloppy,
maybe or maybe not worse than the alternative (studded with +V's just looks
too redundant).

Someone mentioned feedback paths can be reversed. Setting aside "I know
what you mean", would this control circuit be acceptable to mirror, just
because it's a feedback circuit? ;-) The obvious answer is, only if the
rest of the loop dominates the circuit.

Let me add some really simple points.

: +V15
: |
: ,-------+
: | |
: | \
: | / R2
: \ \
: / R3 / C1
: \ | ||
: / +---||---OUT
: | | ||
: | |
: C2| |/c Q1
: || +-----|
: IN---||---+ |>e
: || | |
: | |
: \ |
: / R4 |
: \ \
: / / R1
: | \
: | /
: | |
: +-------'
: |
: gnd
:
: FIGURE 1

This is a very basic, 1st year degenerative ac-coupled
voltage amplifier circuit. I don't like the way it is
diagrammed. Not because I can't instantly recognize it
today. But because I can remember what it looked like to me
when I was first looking at such things and trying to
understand them (I've never taken a single course on
electronics in my life -- not then, not since.)

At the time, I was looking at publications like Popular
Electronics back around the early 1970's. I would see the
wires going from the top of R3 to the top of R2 and would
incorrectly imagine there was some kind of signal there that
I didn't understand. It was only _later_, in one of those
random insights that sometimes dawns on one, that I suddenly
realized that a rail is a rail is a rail and that signal
doesn't happen there. Can't, one hopes most of the time.

Suddenly, I decided to redraw it this way:

: +V15 +V15
: | |
: | |
: | \
: | / R2
: \ \
: / R3 / C1
: \ | ||
: / +---||---OUT
: | | ||
: | |
: C2| |/c Q1
: || +-----|
: IN---||---+ |>e
: || | |
: | |
: \ |
: / R4 |
: \ \
: / / R1
: | \
: | /
: | |
: | |
: gnd gnd
:
: FIGURE 2

Once I did that, the _wires_ no longer made me think about
signal. I could easily see that these were _fixed_ values
where I could _completely_ ignore the underlying "connection"
to the rest. It allowed me to isolate my thinking into much
smaller bits to analyze individually. And that was a very
sudden and very beneficial insight. Keep in mind I had no
one to talk to, no one to ask questions, no one to _give_ me
this insight. I had to find it on my own.

Once I started redrawing things according to this new rule, I
was in high cotton, indeed. Suddenly, circuits that had
seemed so far, far beyond me, were much more accessible.
Because I could divide and conquer and didn't need to go
tracing my fingers around.

Today, I have other reasons now, though. For example,

: +V15
: |
: |
: |
: \
: / R5
: \
: /
: |
: ,-------+-------/ /---------'
: | |
: | |
: | \
: | / R2
: \ \
: / R3 / C1
: \ | ||
: / +---||---OUT
: | | ||
: | |
: C2| |/c Q1
: || +-----|
: IN---||---+ |>e
: || | |
: | |
: \ |
: / R4 |
: \ \
: / / R1
: | \
: | /
: | |
: | |
: gnd gnd
:
: FIGURE 3

Assume that break in the line to R5 makes it so that R5 isn't
immediately visible on the sheet. There is much more
circuitry there and R5 is ... somewhere. Now I have to go
and trace that R2/R3 shared node around to find out if it
goes to a rail or something else, like R5. I shouldn't have
to do that, if it goes to a rail. That line might instead
have been bused over to a +15 voltage source, for all I can
tell, but I'd have to trace it out to find out, if so.\

It's just WRONG to do that. I take a second or two or three
more of my time. Besides that, the wires just lay all over
the place, distracting where they shouldn't when I'm tracing
some _other_ line. And I don't appreciate the waste of my
time for silly things that do NOT affect the meaning of what
is going on locally.

There are times when it is _important_ to bus a rail. But it
needs good justification on some important issue worth the
cost of readability.

Now you might argue with FIGURE 1 and my statement about
having to trace wires elsewhere, telling me that FIGURE 1
doesn't require that and any idiot needs go no further than
what they see right there to know exactly what is going on.
But if you say that, remember my own story when I was first
just starting to try and learn some electronics on my own and
my own confusion imagining that _every_ wire was meaningful
in some way to understanding what was going on; that signals
passed along all wires in some way that I needed to fathom.
Put yourself into those shoes for a moment, too. It's not
easy. Not even for me, trying to remember what it was like.
But I remember enough that I can recall the sudden kicking
myself in the head once it dawned on me. I know that it made
a difference to me then to redraw, in order to understand. A
BIG difference. Not small.

Jon