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Sawtooth generator with PNP transistor

Discussion in 'General Electronics Discussion' started by kingh12, Mar 26, 2013.

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  1. kingh12

    kingh12

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    Mar 26, 2013
    Hi,
    I've been lost in a big trouble with the capacitor charging. First let me summarize you how does this circuit works. When the positive square wave signal reaches pnp transistor, the transistor becomes reversed biased and it doesn't work. By time time the transistor doesnt work, the capacitor starts to charge through DC power supply until negative square wave signal comes. When the negative signal comes, transistor starts to conduct and the voltage charged on the capacitor discharges rapidly. So, we get the sawtooth signal on output. This is the purpose of this circuit.

    My first question is the capacitor charges by the DC power +12V? I mean when we used the formula Vc(t)=V(1-e^-t/RC) , the symbol "V" is my DC power +12V? Or the emitter voltage Ve? Or the voltage on 15k ohm resistance?

    If the answer is 12V, when I used the formula for 47nF capacitor, I found that the capacitor must be charged until 6,02V. But when I praticcally observe this situation on ossiloscope the signal on the capacitor reaches rapidly to 4V and stays on 4V until the transistor starts to conduct.This means capacitor reaches its high voltage which is 4.
    How can this happen? If it will become to its high voltage doesnt it have to be 12 V?
    Here is the circuit of my project on attachment

    I will be very glad if you solve my problem. Thanks
     

    Attached Files:

  2. BobK

    BobK

    7,682
    1,688
    Jan 5, 2010
    Your circuit is basically an emitter follower. That means the voltage at the emitter will follow the voltage at the base + about 0.6V. The 1M resistor biases the transistor into the linear region. If you take out the input pulse, I get the emitter at 3.4V. Now you couple a 1V pulse to the base via a capacitor. This will change the emitter voltage by, surprise 1V, since an emitter follower has no voltage gain. And this is about what you are seeing too, the 4V limit.

    Change your pulse to go from 0V to 12V and it works the way you expect. Here is my simulation:

    sawtooth.JPG

    When the input is high, the transistor is off and the capacitor charges slowly through the 15K. When the input goes low, the transistor is on, and the capacitor discharges rapidly.

    Bob
     
    Last edited: Mar 26, 2013
  3. BobK

    BobK

    7,682
    1,688
    Jan 5, 2010
    Duplicate.
     
  4. kingh12

    kingh12

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    0
    Mar 26, 2013
    Thanks for your reply Bobk. I just look to your simulation. There will be another situation too. When I expect 6.02 V capacitor charged voltage from the formula this means it is greater than my input pulse signal. So the transistor must be conducted that time because my p-n link becomes forward biased . By the time 6.02V-4V= 2.02 V passes throught the transistor. Am I right?
    And based on your message, does it mean, the emitter voltage limits the capacitor charging voltage level?
     
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