Rough and ready hold off timer delay

I have the following problem:

If Input=High the Output=High
when input falls to LOW then start a timer delay (15 mins) to prevent output
going high for the period of the delay.

At end of time period release time lock and allow a Input=High to make
Output=High

The tolerance of the timer isnt important i.e. +/- 10% would work ok.

Any ideas anyone?

 

-
-If Input=High the Output=High
-when input falls to LOW then start a timer delay (15 mins) to prevent output
-going high for the period of the delay.
-
-At end of time period release time lock and allow a Input=High to make
-Output=High
-
-The tolerance of the timer isnt important i.e. +/- 10% would work ok.
-
-Any ideas anyone?

question 1: at the end of the 15 minutes if IN=LOW then do you start another
timer cycle?

question 2: voltage values for HI/LO?

You'll get all of the usual suspects:

1) Use a 555 in one shot mode with a ~ 15 minute delay. You'll need an
inverter for the output (because it's the inverse of the input signal) and
you'll need to gate the input trigger so that it goes high as soon as the
output goes low. So at minimum a 555 and a quad NOR/NAND gate for the
required gating/inverting.

2) Use a microcontroller. A single 12F629 would knock out the whole project
in short order.

3) A gated counter.

BAJ

 

You'll get all of the usual suspects:

Which one's Kaiser Sochay (sp?)? I'm guessing 2.

 

------------------
Do it the antique discrete way, the input one-shots on the falling
edge a pulse that resets the counter, which counts up for 15 minutes
off a clock circuit and when the counter is X counts (15 minutes)
an AND gate of the counter's output bits goes HI and stops the clock
till the next falling edge.

I'm sure others will offer CMOS 555's and microcontrollers.

-Steve

 

If Input=High the Output=High when input falls to LOW then start a timer
delay (15 mins) to prevent output

Output=High

Having trouble acheiving this with the 555 as I need to start to the timer
circuit when the input falls to low, yet the 555 requires a high input on
pin 2 to function. It is easy to start the timer when the output goes high -
but I cannot see how to do it the other way round.

Would it be easier to use an opamp as a timer? Feed in a reference voltage
on the -side, and a resistor and capacitor to the +side. The capicator will
charge through the resistor and the voltage at the opamp will increase.
After the delay required (adjustable by changing the capacitor/resistance)
the opamp will produce a high output.

If a transistor is fitted between the capacitor and resistor divider, and to
ground when the input is high to the transistor the voltage at the opamp
will be forced low.

Once I have an output that is high or low when the timer is on (i.e stays
high for 15mins after the input falls to low) it is just a simple logic gate
to control (i.e input=on and timelock=off)

 

---
The 555 requires a low pulse on pin 2 to start the timer, and that
pulse must be shorter than the output pulse in order for the 555 to
operate properly.

From your post it seems this is what you want:
______ ___________________ _____
IN |_| |________________________|

|<----15 MIN---->| |<----15 MIN---->|
_______ ____ _____
OUT |________________| |________________________|

---
If I read it right, the problem with that approach is that, unless you
lock out the input pulse/level during the timeout period, you'll wind
up retriggering the timer whenever the input goes low and the timeout
won't start until the input goes high.

If you want to use a 555, use a CMOS version like a 7555 and arrange
the circuitry like this:


Vcc Vcc
| 7555 |
[10K] +-------+ [10M]
| |__ _| |
+--------O|TR D|O--+
| |_ | |
[0.1] Vcc--O|R TH|---+
| | OUT|---|--[INV]---A
| +-------+ | AND Y---->OUT
IN>---+---------------------|----------B
|+
[82µ]
|
GND

Threshold current for the 7555 is 500pA max with Vcc = 16.5V, so the
main problem you're going to have with getting 15 minutes out of it is
the leakage of the timing cap. You can use a tantalum electrolytic
instead of aluminum to get lower leakage, but in any case you'll have
to fiddle with the value of the timing resistor (10M) to adjust for
the tolerance and leakage of the cap.

Since you need an AND to generate the output you want and you need to
invert the 555's output, you can do it with a single NAND (HC00, for
example) like this:



7555OUT>-----+--A1
| Y1------A2
+--B1 Y2--+--A3
IN>------------------------B2 | Y3--+--->OUT
+--B3 |
| |
+--A4 |
| Y4--+
+--B4

Paralleling the third and fourth gates will allow you twice the output
current and keep from wasting any gates.

 

If I've understood correctly, then this simple circuit using one
commonplace IC should do it:
http://www.terrypin.dial.pipex.com/Images/PeteProblem.gif

The breadboarded results of that (using much lower RC values to speed
up testing) are illustrated here:
http://www.terrypin.dial.pipex.com/Images/PeteWaveforms.gif

As you see, mono output periods were well within your suggested 10%
tolerance.

Images also attached in alt.binaries.schematics.electronic

 

Thanks for the help.

Not exactly what I was thinking, but your circuit should be easier as it
combines two operations!

I intended to start the timer when input falls to low, then combine the two
logic signals to control the output - i.e input=High and Timelock=high. Thus
the input would not be able to go high during the lockout time.

According to your waveforms the circuit combines both these functions. The
input can be high, but when the input falls to low it the output is
prevented from going to high again until AFTER the time period.

I played around with this circuit using Crocodile Technology and couldnt get
it to work as it should. Eventually after experimenting I have got the
circuit to work (using indestructable components). The NAND gates do not
like the negative voltage that they experience when a trigger input is
applied.

In addition, I notice that the input trigger must be applied for a
substantial period if the circuit is to recongnise the trigger (i.e I short
trigger is not recongised)

Any idea what I might be doing wrong to get your circuit to work?

 

Afraid I don't follow. How are you applying the trigger? Are you
saying it is below 0V? How? In what way do the NAND gates "not like
the negative voltage..."?

What do you mean by 'substantial'? As you see, my trigger pulses were
around 100 ms. That was from a push button (connected from pin 2 to
0V, with a 10k resistor from pin 2 to Vcc). But that standard circuit
works with any -ve going pulse, from a few microsecs up.

If you've actually breadboarded it exactly as shown, and applied -ve
going DC pulses to pin 2 as shown (i.e. Vcc to 0V and back), then it
should work as it does here. What values of R1 and C1 are you using?
If C1 is polarised, do you have it correct way round? Are you using
all 4 gates? If not, have you tied unused ones to 0V?

 

I played around with this circuit using Crocodile Technology and couldnt
get
I have just set the circuit up again using Crocodile Technology. I have
posted a copy of the schematic in binaries.

is below 0V? How? In what way do the NAND gates "not like

I am using a 10v input via a push to make switch to apply the trigger, and
using 10v supply voltage to the NAND gate. Unless undestructable components
are selected, the second NAND gate blows in the simulation with the message
"The pin voltage was taken below the negative supply voltage by 9.2604v. The
maximum rating is 1v". When a trigger voltage is applied to the first NAND -
there is a negative voltage on the right side on the cap.

around 100 ms. That was from a push button (connected from pin 2 to

works with any -ve going pulse, from a few microsecs up.

When the input is made high, unless the input remains high for 2 seconds the
trigger isnt activated, after I a closer look, When the circuit is
stabalised (i.e powered up a while) the capacitor charges to show a 10v
charge across it. In the simulation I have used a 440cF cap, and 10k res.

When the input trigger goes high, the cap starts to discharges through the
resistor, when the input trigger goes low again the capacitor start to
charge again up to 10v. However the timer will only trigger the second NAND
gate once the input trigger goes high and the voltage across the capacitor
is drops to 4v.

If the input trigger is operated when the voltage across the cap is about 4v
the the trigger works ok. but if the cap is allow to charge to 10v - then
in takes another 2 second input to bring the voltage back down to 4v to
trigger the circuit. If the cap/resistor values are changed to give a 15min
timer, then the time needed to hold the trigger down would become more than
substantion..

I must be doing somthing wrong. can anyone see it?

 

For a start, breadboard the actual circuit - with the trigger set up
properly as I described. You currently have no resistor to Vcc. And is
your supply properly regulated?