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Ring Counter

Discussion in 'General Electronics Discussion' started by Toraora, Mar 18, 2012.

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  1. Toraora

    Toraora

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    Mar 18, 2012
  2. timothy48342

    timothy48342

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    Nov 28, 2011
    I'm no expert in this area, so I'm just musing a bit about how I THINK IT SHOULD work...

    If you look at the diagram on page 4 of the pdf you linked. It seems like if you just connect the output "Od" to the "shift right serial input" and connect the output "Oa" to the "shift left serial input" it ought to work circularly. (basically the bit that would normally be discarded during a shift get routed back arround as if it was coming in as a new bit from the outside.)

    --tim
     
  3. Toraora

    Toraora

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    Mar 18, 2012
    Thanks.

    I got it to work (with one hitch) by connecting Od to the "S1" mode control input. The problem is that, when first powering the IC, all of the outputs start at 0, and the circuit does no good shifting around a bunch of zeroes. How can I get the register to automatically load a 1 into one of the outputs without manually detaching a wire?
     
  4. timothy48342

    timothy48342

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    Nov 28, 2011
    um... S1 mode control and S0 mode control are the inputs that make the shifting take place arn't they? One would cause a shift left and the other a shift right? I would think you need those available to make the shifting happen. (without disconnecting a wire)

    As fas as how to get the 4 bits of data in there in the first place, there are parallel inputs. A, B, C and D along the left side of the page 4 diagram. You would set those inputs each to a one or zero. (hi and lo?) and then "activate" the chip to read the 4 parallel inputs. (Sorry, I don't know how to "activate it") le' me go have another look...
    --tim
     
  5. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    25,359
    2,755
    Jan 21, 2010
    You think correctly.

    Another thing that can be done is to pass the inverted output of a shift register back to the input. This makes a totally different device, a "twisted ring counter". Also a very interesting device (for a whole host of reasons)

    edit: the twisted ring counter can be initialised to all zeros and still work too -- but it's almost certainly not what you want.
     
  6. timothy48342

    timothy48342

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    Nov 28, 2011
    ok. I'm looking at the top of page 2, a chart called function table.

    Based on line 3 it looks like any time that "clear, "s0" and "s1" are all high and a clock cycle happen (clock transitions from low to high) that the values of inputs A, B, C, and D are read and all 4 bits set to that.

    One thing, though...
    If yhou think you got it working and then something goes wrong, recheck this part.
    That does not seem right to me.

    -tim
     
  7. Toraora

    Toraora

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    Mar 18, 2012
    I thought only one of them was used at any given point in time, S0/S1 set the direction of the shift?

    I currently have:
    VCC <- 5V
    B,C,D - GND (leave A high)
    S1 - GND (S1 low, S0 high)
    Serial R <- Od

    This setup only works if I first disconnect S1 from ground (to have it read from A,B,C,D). Otherwise, all outputs remain low.
     
  8. timothy48342

    timothy48342

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    Nov 28, 2011
    You mean only use one of the serial inputs? Sure only connect "serieal right input" to Od if your only shifting to the right and you want it to be circular to the right. If you want it to also have the ability to be circular to the left, then you would connect Oa to "serial left input" but it's not needed for just circling one direction.

    You mean only use either S0 or S1. That was confusing to me at first. I would have expected that there would be an input to command it to shift right and another input to shift it left, (I expected an "SR" and an "SL") but that seems not to be the case. Instead there are 4 modes controled by S0 and S1:
    Code:
    S1    S0    mode
    L     L     do nothing (stop shifting, ignore clock)
    L     H     shift bits right
    H     L     shift bits left
    H     H     discard stored bits and re-read from 4 inputs A,B,C,D
    At each clock cycle one of the above 4 things will happen.
    ok so what's happening there. You have s1 low and s0 high, so it is in the "shift right" mode and if it contains all zeros it just keeps shifting the zeros on each clock cycle. (uselessly of course)

    Then you disconnect s1 from ground bringing it high which is the "read from input' mode and it stops shifting and reads HLLL (for ABCD)

    Then when you reconnect s0 to ground it starts shifting agian. (circularly) LHLL, LLHL, LLLH, HLLL etc.

    I think you are using it right and you are using the parallel A input as a way to seed the data with a single "H"

    You'll have a single H circling round and round. Does that work for your application?

    Also... What is your application?

    --tim
     
  9. Toraora

    Toraora

    5
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    Mar 18, 2012
    I have that all working, but my main problem was that upon power up I had to
    Is there any way to do this automatically and not manually or by software?

    I'm also just learning these circuits. I went to Fry's and picked up a few ICs that looked interesting.

    Thanks for the replies
     
  10. timothy48342

    timothy48342

    218
    0
    Nov 28, 2011
    Shouldn't be too tough, and I wouldn't be surprised if someone can come up with something better than this, but here is one idea.

    Description:
    Connect s1 to vcc, but through a capacitor and resistor in series. The resistor would be small enough that s1 is high when the cap is uncharged. (on powerup) Include a resistor to ground, after that so that after the cap fills up, s1 goes low and stays there. A third cap bypasses the cap, so that the cap can drain when the power is off.
    See attachment. (C1 is labled, but ignore that. I forgot to delete the label when I made the pic.)

    As far as the sizes of R1,2,3. I'm not sure how to start, but here are the constraints.
    R3 should be large compared to R2. (10x larger should be fine, maybe 5x)
    R2 should be large compared to R1( 5x to 10x again)
    The R1, C1 time constant should be way more than the lenth of one clock cycle.
    The R3, C1 time constant will be approximately the amount of time you have to leave the device off to reset the data bits to HLLL
    For instance, if R3 is 100 times the value of R1 then the reset time will be 100 times as long as a clock cycle. If your clock cycle is .001 sec, then you will have to stay powered down for at least .1 sec for to reset. There should be a very wide range of values that work.
    I suppose I'm ignoring any current draw into S1 itself, but if it's quite small, compared to current through R1 on power up, then it can also be ignored. If it's not small enough, then it might further constrain the value of R1. (R1 would have to be small enough that the current through R1 greatly excedes the current draw into S1)

    (At the risk of being redundent, heres the full strategy)
    On power up, C1 can be assumed empty(due to R3), and S1 sees close to Vcc. (r2, r3 are large compared to R1 so they are ignored for that.)
    Then after one or more clock cycles, c1 fills up enough that R2 controls what is going on. (R3 is large compred to R2 so it can be ignored for that)
    So S1 goes low and stays there as long as the power is on.
    When you power down, no more current flows through R1 or R2, so R3 is the only thing that matters and the cap discharges so its ready for next time.

    Basically I like to ignore things when possible, don't I?

    If something doesn't make sense, let me know, but if you get the general ideal then just play around with the values until you find what works. I think you'll have A LOT of leeway in value selection with this design.

    --tim
    (hope the attachment worked)
     

    Attached Files:

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