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Regenerative Latch

Discussion in 'Electronic Design' started by Sanjayan Vinayagamoorthy, Sep 8, 2003.

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  1. Hello,

    I am trying to simulate a regenerative latch using winspice
    (www.winspice.com) but I am having difficulty in trying to get any
    out. My netlist is as follows:

    *Regenerative Latch

    *** Top Level Netlist ***

    *Left Hand Side Inverter
    M4 5 2 101 101 CMOSNB L=5u W=15u
    M1 3 2 100 100 CMOSPB L=5u W=44u

    *Input NMOS
    M3 4 7 5 101 CMOSNB L=5u W=15u

    *Latch NMOS
    M2 3 6 4 101 CMOSNB L=5u W=15u

    *Right Hand Side Inverter
    *M8 9 3 101 101 CMOSNB L=5u W=15u
    *M5 2 3 100 100 CMOSPB L=5u W=44u

    *Input NMOS
    *M7 8 10 9 101 CMOSNB L=5u W=15u

    *Latch NMOS
    *M6 2 6 8 101 CMOSNB L=5u W=15u

    *Power Supply
    VDD 100 0 DC 3.3v AC 0 0
    VSS 101 0 DC 0v AC 0 0

    *Input
    *VIN 2 0 0v
    VIN 7 0 pulse(-2.5 2.5 0 .1ns .1ns 20ns 40ns)
    VIP 10 0 pulse(2.5 1.5 0.1ns 0.1ns 15ns 30ns)
    VLatch 6 0 pulse(0 3.3 0 0.1ns 0.1ns 20ns 40ns)



    *** WinSPICE script to automatically run the plots
    ..control
    ..endc

    *.NODESET v(2) = 3.3 V(3) = 3.3

    <sniped out the models of MOS transistors>

    I have no idea what to do next? Is there a way of getting this to
    simulate?
     
  2. Jim Thompson

    Jim Thompson Guest

    What error messages are you getting?

    ...Jim Thompson
     
  3. Hello,

    Thanks for responding. I get the following error message:
    Warning: vlatch: no DC value, transient time 0 value used
    Warning: vip: no DC value, transient time 0 value used
    Warning: vin: no DC value, transient time 0 value used
    Note: Starting Gmin stepping
    Warning: Gmin step failed
    Warning: Gmin stepping failed
    Note: Starting source stepping
    Warning: Source stepping failed

    doAnalyses: Convergence problem: Iteration limit reached - see
    '.option itl5' setting

    In case you are not sure how the circuit looks like,


    Vdd Vdd (100)
    --------------------------------
    | |
    M1+-|| ||-+ M5
    <-|| ||->
    +-||-| |-||-+
    | | | |
    o o---------o
    | | | o
    o---------o |
    | | | |
    (6) ||-+ M2 | | M6+-||
    Latch ||<- | | ->|| Latch(6)
    -------||-+ | | +-||-------
    | | | |
    (4)| | | |
    | | | |(8)
    ||-+ M3 | | M7 +-||
    (7)VIN ||<- | | ->|| VIP
    ------||-+ | | +-||-----
    | | | |
    | | | |
    (5)| | | |(9)
    | | | |
    M4 +-|| | | ||-+ M8
    ->|| | | ||<-
    +-||-| |-||-+
    | (2) (3) |
    | |
    | |
    ------------------------- VSS(101)
    created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de

    This is what I tried to mimic. Note that node numbers are in
    parentheses.
    (Basically the two gates of the inverter pair are precharged to VDD
    when latch is low. I should add a couple of PMOS transistors (gates
    connected to latch), that precharge the gates to VDD when latch is
    low.

    Regards,
    Sanjay
     
  4. Jim Thompson

    Jim Thompson Guest

    When "Latch" is LOW you have a float condition.

    ...Jim Thompson
     
  5. Jim Thompson wrote...
    I think there's a fundamental problem that can occur
    when designing and drawing an ASCII schematic online,
    namely over-simplification. The sheer difficulty of
    getting the drawing properly in place on the screen
    mitigates against its being sufficiently complete for
    proper operation.

    Thanks,
    - Win
     
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