Re: Intel details future Larrabee graphics chip

[Kim Enkovaara]

When the total sales of something is likely to be 10 units, a 100K
tool just for that project does make cost an object but this isn't the
only nor really my biggest problem with them.

Fortunately the 3rd party synthesizers for FPGAs are not that expensive.
And third party tools offer easier way of handling many different chip
families.

Imagine the product has been in production for 10 years and somebody
discovers a (gasp) bug. You now have to fire up that old tool and fix
the bug. With rented software you can't just do that this means that
there will be the urge by management not to fix that bug and a delay
in fixing it.

You have the same problem with the "free" software also. Many of them
used time based licenses, and also the windows based software might
be hard to get working after 10 years. Nowadays virtual machines
are really helpful in booting up the really old tools tough.

If you still have some software from the old tool vendor, usually it's
quite easy to get temporary licenses for the really old tools. Some
time ago I saw how one vendor managed to even find installation media
for a tool from the middle of 90s. And they also created new licenses
for the tool. No sane person would use the tool for new development,
so the keys were easy to get.


--Kim

 

[Ken Hagan]

If I needed to know, I'd probably use Performance Monitor in Windows
XP.

Straight out of the box, performance monitor doesn't have a suitable
counter for this. I believe sys-internals do a widget that exposes
values from the RDPMC instruction. That might help if there were a
suitable performance counter to report.

But is there? There are certainly counters for cache misses, but those
don't necessarily affect performance in an OoO processor. I suppose
you could quote the "total number of instructions retired" value as
a proxy for "useful CPU work done", but the 100% level for that depends
on the available ILP.

I suppose part of the problem is the lack of a suitable definition for
when the CPU is "usefully busy".

 

[MooseFET]

MooseFET wrote: [....]

Imagine the product has been in production for 10 years and somebody
discovers a (gasp) bug.  You now have to fire up that old tool and fix
the bug.  With rented software you can't just do that this means that
there will be the urge by management not to fix that bug and a delay
in fixing it.

You have the same problem with the "free" software also. Many of them
used time based licenses,

Yes, I include the "free" license in with the rented.

and also the windows based software might
be hard to get working after 10 years. Nowadays virtual machines
are really helpful in booting up the really old tools tough.

I still have a machine that runs windows 89 and I have "bochs". I
also have the ability to run a machine in DOS 5.0 and "dosemu".

If you still have some software from the old tool vendor, usually it's
quite easy to get temporary licenses for the really old tools. Some
time ago I saw how one vendor managed to even find installation media
for a tool from the middle of 90s. And they also created new licenses
for the tool. No sane person would use the tool for new development,
so the keys were easy to get.

What about when the vendor of the tool has gone out of business? I
have a perfect record so far on the chips. Every CPLD I have selected
for a product has gone off the market. I selected the Philips "cool
runner" for example.

 

[JosephKK]

|> >In article <[email protected]>,
|> >|>
|> >|> > |> The IEEE format is pretty well thought out.
|> >|> >
|> >|> > That is a matter of opinion. A large number of experts, in many
|> >|> > aspects of numerical computing, disagree.
|> >|>
|> >|> What is wrong in your opinion and how would you improve it?
|> >
|> >This has been described ad tedium. I would start by defining a
|> >clear, consistent objective and work from there. It doesn't
|> >matter so much WHAT the objective is, provided that it HAS one.
|>
|> It has been some time since i have fussed with this. Where do i find
|> discussion the improvements you are talking about?

I wasn't describing specific improvements. Anyway, probably on the
archives of this group, or comp.arch.arithmetic. Google groups
seems to be on the blink, as it gets only one hit for "IEEE 754"
on the latter, and for "IEEE" and "floating-point" on the former,
which I have difficulty believing!

There was also an IEEE 754R mailing list, which may be archived
and accessible - see http://www.ucbtest.org.


Regards,
Nick Maclaren.

Looks like some nice stuff there, it will take me a while to dig
through it all.

 

[JosephKK]

Were they all different subsets of IEEE (which is what we were discussing)?

Wilco

Actually none of them were. They predated IEEE 754.

 

[JosephKK]

|>
|> >Also, you are ignoring the fact that almost all programs use languages
|> >other than assembler nowadays, and the IEEE 754 model is notoriously
|> >incompatible with the arithmetic models used by most programming
|> >languages. That, in turn, means that two compilers (or even options)
|> >on the same hardware usually give different results, and neither are
|> >broken.
|>
|> This one is new to me. Where do i go to find backup? The magnitude
|> of the claim does sound a bit extreme.

The relevant language standards? Seriously. For 'clarification',
you will need to read the archives of the SC22 mailing lists.

To save you time: in Fortran, look for the rules on expression and
function evaluation and, in C/C++, the rules on side-effects and
the INCREDIBLY arcane syntax and semantics of preprocessor versus
compile-time versus run-time expressions. And remember that flag
handling is NOT optional in IEEE 754, but a fundamental part of its
design, as Kahan points out.

|> >There are a lot more than five variants in use today, even just at
|> >the hardware level. Actually, Intel has at least three, and quite
|> >likely more.
|>
|> Some pointers to more details please.

Look at the IEEE 754 specification on the handling of underflow
and NaNs, and then study Intel's architecture manuals VERY
carefully, looking for x86 basic FP, MMX, SSE, IA64 and optional
variants. Then look at the MIPS, SPARC, PowerPC and ARM
architecture manuals.

Then laugh, cry or scream, according to taste.


Regards,
Nick Maclaren.

It is going to take me a while to get and go through all that.
Meanwhile, i will keep asking questions to direct my study.

 

[MooseFET]

+---------------
| What about when the vendor of the tool has gone out of business?  I
| have a perfect record so far on the chips.  Every CPLD I have selected
| for a product has gone off the market.  I selected the Philips "cool
| runner" for example.
+---------------

Uh... Don't you mean *Xilinx* "CoolRunner"? That line was still quite
active the last time I designed with them (within the last year)!!

No I really do mean the Philips cool runner. Philips sold the business
to Xilinx and went out of the CPLD business. Xilinx only manufactured
the 3V part and didn't make the 5V one I had designed in. The result
was that my design was stranded as soon as we burned up the stock.

Fortunately, Altera still makes a 5V part with the same pin out.
Altera doesn't suggest it for new designs but at least the product can
continue for a while.