M
MooseFET
- Jan 1, 1970
- 0
Then you have something wrong in your coding style. Normally if some
portability is taken into consideration during design, porting takes
few days to get first impressions.
I wasn't referring to just my code when I said "seen".
Do you use the assignment of the "Z" value to cause a tri-state?
Quartus doesn't compile them.
Usually what is needed is some
tweaking of attributes in inferred memories, new clocking scheme
(PLL etc.) and maybe some IO pin instantiations if DDR or very
high speed signaling is used. For some higher level IP (tranceivers,
PCI express etc.) more effort is needed, but that can be handled
by portability layers.
With third party synthesizer scripts need only minor changes. And even
with the integrated ones usually some editor tweaking can be used
to get most of the scripts converted. STA is the most painful thing
to convert, that will take some time. But that is only loosely part
of the code, and Synopsys SDC format is gaining ground in FPGA tools
also.
We were talking of the tools that are free or low cost that come from
the makers of the chips.
It is quite normal to code the FPGA to support many different chips
and keep the vendors fighting with price to the end and select the
one that was the cheapest
I really don't care which chip is the cheapest. In the market I'm in,
nearly all electronic designs are a "cost is no object" sort of
thing. The first 3 tings on the list are reliability. Then comes low
power and light weight.