# RC circuit

Discussion in 'Electronics Homework Help' started by seymourfroggs, Sep 29, 2014.

1. ### seymourfroggs

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Sep 29, 2014
Hi

With an RC timing circuit, when is the signal High and when Low?

Say I have a Gate, (eg ic4093) with a + feed to Pin 1. I have a + feed to Pin 2, but then drop it low for a short (but variable) time.
The output (PIn 3) will go High during this time (call the time interval here "t").

Now this + output goes to Ground via a Resistor followed by a Cap, and there is a lead to a second Gate (Pin 5 on the 4093).
Q: is the feed to Pin 5 High during "t", or does the Cap "absorb" the current, meaning the signal is Low during "t"? I realise this "t" is not the same as time to Pin 5: this required time is the CR product. But I'm confused as to whether the R + Cap is allowing a Pos delay, or creating a Neg one.

Also, does it matter where the take off to Pin 5 is? I see circuits with CR in series, and the feed to Pin 5 above or below or between the Cap and R.
And also, with the R going straight to Ground but the Cap between this and the Pin 5.
(I would expect that if ground is treated as an electron source, the capR would "slowly" develop a + charge on the "upper" plate, and only then would a current (this time meaning pos to neg) flow to the Pin5). So the timed signal would be Low. Yet the schemes imply timed High.

(Apologies for such an elementary Q)

Last edited: Sep 29, 2014
2. ### KrisBlueNZSadly passed away in 2015

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Nov 28, 2011
Hi there and welcome to Electronic Point

A diagram would clarify what you're asking.

If you have gate A output connected through a resistor to gate B input, and a capacitor from gate B input to 0V, this forms an R-C delay. When gate A output goes high, the capacitor will start to charge through the resistor, and the voltage across it (which is also the gate B input voltage) will increase, following the standard resistor-capacitor charge curve (Google those keywords for details).

At a certain point, this risng voltage will cross the rising threshold of the gate B input, and gate B will regard that input as high. The rising voltage threshold varies depending on the manufacturer of the 4093 and also manufacturing tolerances. But the R-C circuit will always introduce some delay.

If the gate A output goes low before the gate B input voltage reaches the rising threshold, the capacitor will discharge through the resistor back towards 0V and gate B will not detect a high input voltage.

If this doesn't answer your questions, post a schematic, preferably with input waveforms included.

3. ### seymourfroggs

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Sep 29, 2014

Thank you!

This circuit works but HOW does it work??
OPTO gives a short intermittent voltage drop as the flywheel mirror rotates past (existing voltage held to Pin 2 drops to ground; not shown).
Now, is Pin 3 going to develop a High signal (since 1 is High) - or does the Cap "absorb" this giving a Low (until its charged) ?
And the OPTO meanwhile has "gone open" so Pin 2 gets a + charge. Which means Pin 3 goes Low, but the 15n/47K might still be dealing with the prior High.
I'm confused.

4. ### Colin Mitchell

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Aug 31, 2014
The first thing you have to do is draw the circuit as GATES. Not "block diagrams."

5. ### seymourfroggs

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Sep 29, 2014
@Colin Mitchell

May I put it more simply?
If I had a pulse generator putting out every second a + signal lasting 100ms, and linked to a Light (say) then a resistor, then to O v, the light would go on for 100 ms (assuming suitable current etc).

If I attach a side link via a capacitor to O v, (and say the RC time gives 10 ms), does the light NOT go on for 10 ms, then stay on for 90 ms?

Thank you.

6. ### KrisBlueNZSadly passed away in 2015

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It would help if you drew the NAND gates inside the 4093 packages.

The circuit you have there is called a C-R "differentiator".

At idle, pin 3 is low, and pin 5 is also low because the 47k resistor pulls it low. So the 15 nF capacitor is discharged, i.e. it has no voltage across it.

The characteristic of a capacitor is that the voltage across it remains at its present value unless current flows into or out of the capacitor. If current flows, the voltage across the capacitor changes at a rate determined by the amount of current.

When pin 3 goes high, there is initially no voltage across the capacitor, so the capacitor pulls pin 5 high as well. This is inverted by gate B, so pin 4 goes low, and this is inverted by gate C, so pin 10 goes high.

Assuming pin 3 remains high, the capacitor will start to charge through the 47k resistor. This means that the voltage on pin 5 will decrease, because pin 5 is being pulled down towards 0V by the resistor.

After a certain amount of time, the voltage at pin 5 will have dropped far enough that the 4093 regards pin 5 as low. Pin 4 will go high, and pin 10 will go low.

So the combination of the capacitor and resistor converts the wide positive pulse at pin 3 into a narrower positive pulse at pin 10. The pulse at pin 10 goes high immediately when pin 3 goes high, but it returns low again after a time determined by the product of R (47 kΩ) and C (15 nF).

When pin 3 goes low again, the capacitor discharges through the resistor so there is no voltage across it. Like the charge-up of the capacitor, this discharge takes a certain amount of time; often a diode is added to the circuit to help the capacitor discharge quickly, but that's not needed in your circuit because the pulses at pin 3 are widely spaced.

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7. ### Colin Mitchell

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Aug 31, 2014
"When pin 3 goes low again, the capacitor discharges through the resistor so there is no voltage across it."

No.

The capacitor discharges via the protection diode on Pin 5.

"Like the charge-up of the capacitor, this discharge takes a certain amount of time;"

No

The capacitor takes almost NO time to discharge.

You just have to make sure the value of the capacitor and resistor always make the "Fire Pulse" a shorter duration than the "Pulse."

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8. ### KrisBlueNZSadly passed away in 2015

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You're right Colin.

When pin 3 goes low, the capacitor will discharge most of the way through the input protection diode on pin 5, and pretty quickly.

9. ### seymourfroggs

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Sep 29, 2014
How do you mean, "pulls"? Pin 5 is low to start because its connected to 0 V.
This is where I get lost. In my evidently weak understanding, when Pin 3 goes high (call it a + charge), the "upper plate" of the cap begins to accumulate + charge. The lower plate will accumulate opposite charge, namely low. How does that "pull (!) pin 5 high" - ???
Or does the lower plate, by accumulating - ve charge, having been "neutral", cause + charge to flow away, causing Pin 5 to "see"/receive a + charge?
( quoting fixed -- KrisBlueNZ )

10. ### KrisBlueNZSadly passed away in 2015

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OK, forget positive and negative charge for the moment. First, understand the capacitor's behaviour. Then you can get into its internal physics.

The most basic definition of the behaviour of a capacitor is:
• It keeps the voltage across its terminals constant, unless there is a current flowing;
• If there's a current flowing, the voltage across its terminals changes at a rate that is proportional to the amount of current. (And also the capacitance, which we assume is fairly constant.)
This relationship is given by the formula

dV / dT = I / C
where
dV is a change in the voltage across the capacitor (measured in volts);
dT is the time over which that change occurs (measured in seconds);
I is the current flowing into or out of the capacitor (measured in amps); and
C is the capacitance of the capacitor, measured in farads.

So let's try an example. Say we have a 1 farad capacitor, and there's no voltage across it. Now we connect it to a power supply that feeds a constant steady current of 1A into the capacitor. The voltage across the capacitor will increase steadily, at a rate of 1 volt per second. After one second, the voltage across the capacitor will be 1V. After another second, it will be 2V. If the power supply is disconnected, the capacitor will continue to have 2V across it.

(In practice, no capacitor is perfect and there will always be a leakage path where some current will flow, so the capacitor will not hold a charge forever; it will discharge at a rate determined by the leakage current using the above formula.)

Initially when we first turned the power supply ON, there was 0V across the capacitor and this did not change immediately. It started to change immediately, that's all. The voltage across a capacitor does not change instantly - that would require infinite current. It changes at a rate that is proportional to the current. Lower current = slower rate of change of the voltage across the capacitor.

In that circuit, pin 5 isn't "connected to" 0V; there is a resistor in between. When pin 3 is low and the capacitor is fully discharged, pin 5 will also be low, and this condition can continue forever. Once pin 3 goes high, the voltage across the capacitor will not change immediately, so the capacitor pulls pin 5 high. The twice-inverted output at pin 10 also goes high.

Current flows from pin 3, through the capacitor, through the resistor, to 0V and the capacitor starts to charge up.

Because of the direction of current flow "through" the capacitor, the side connected to pin 3 starts to become more positive than the side connected to pin 5. In other words, the voltage on pin 5 starts to drop. At a certain point, the 4093 will regard this voltage as low, and the twice-inverted output at pin 10 will go low.

As long as pin 3 remains high, the capacitor will continue to charge until pin 5 reaches 0V and no more current can flow through the resistor because there is no voltage across it.

Once pin 3 goes back low again, the capacitor is charged up to the supply voltage, so it tries to push pin 5 negative. But pin 5 has input protection diodes that prevent it from going more than about 0.7V negative relative to the 0V rail. The input protection diode conducts, and the capacitor discharges fairly quickly. The discharge time is mostly limited by the output resistance of gate A.

During this time, the capacitor will prevent pin 3 from falling cleanly and sharply. This is undesirable because pin 3 is also used to provide a "hold pulse" signal to the other 4093. This arrangement would probably not be used in a professionally designed product.

11. ### seymourfroggs

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Sep 29, 2014
Thanks. We're getting there. (I note your end remark: cap will prevent pin 3 from falling cleanly and sharply. Yes, but there'd be a sq wave output at Pin 10, would there not?).
Once pin 3 goes back low again
This is a discharge to Pin 7 and so to O v, thro' internal circuitry?
the capacitor is charged up to the supply voltage, so it tries to push pin 5 negative
Confused again: as Pin 3 goes low ( O v ???), why does that make Pin 5 neg? Is this "more neg" than O v?
In the real world, we have an electromagnetic field across the plates of the cap, with many electrons on the neg (in this case, Ground) side. Is Neg more Neg than Ground?
As Pin 3 goes low ie more neg, are you saying the change in field frees the electrons, or pushes them away to Pin 5? Hence "push".

12. ### KrisBlueNZSadly passed away in 2015

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Yes.
Gate A is used as an inverter. Its input is on pin 2 and its output is on pin 3. So pin 3 goes low when the input signal on pin 2 goes high.
Yes, negative relative to the 0V rail. More negative than 0V. (BTW that's "zero volts", 0V, not "O V".)

Part-way through the high pulse on pin 3, the output on pin 10 goes low, because the capacitor has charged up enough that the voltage on pin 5 (which is being pulled towards 0V by the resistor) has fallen below the falling input threshold voltage of gate B.

While pin 3 remains high, the capacitor continues to charge, and the voltage on pin 5 continues to fall.

Let's assume V+ is 12V and the pin 5 voltage has fallen to +2V. There is 10V across the capacitor, with the plate connected to pin 3 being positive relatve to the plate connected to pin 5. Then, pin 3 goes back low (0V) again.

So gate A tries to bring the positive side of the capacitor down to 0V. The negative side of the capacitor will try to jump down to -10V (relative to the 0V rail). This is what causes the input protection diode in gate B to conduct and clamp pin 5 to about -0.7V.

So pin 3 tries to jump down to 0V but the speed at which it falls is limited, because it has to discharge the capacitor as it falls. The charged capacitor and the protection diode on pin 5 together have the effect of preventing pin 3 from falling steeply and cleanly to 0V because as pin 3 falls, it is discharging the capacitor (through the diode) and this doesn't happen instantaneously. The discharging current is limited by the output resistance of gate A.
Yes. And my description is as much "real world" as the description based on charges on the capacitor plates.
Pin 3 goes low, but the electric field in the capacitor doesn't change immediately. It changes only over a period of time (a very short period of time in this case), and in response to current flow.

When the pin 3 side of the capacitor is driven towards 0V (by gate A's output), the pin 5 side of the capacitor goes negative because of the static electric field across the capacitor. This causes the protection diode in gate B to conduct, forming a path for electrons to leave the plate connected to pin 5. As they leave, the electric field in (i.e. the voltage across) the capacitor drops. But I don't find any of this to be helpful in understanding how the capacitor behaves.

BTW I meant to say two more things about my description.

The example I gave with the 1 farad capacitor was an unusual one; most capacitors have much lower capacitance. Also, charge and discharge currents (in small-signal circuits, at least), are usually a lot lower than 1A. Together this means that capacitors often charge and discharge over shorter periods, or much shorter periods, than one second.

Also, that description with the linear voltage change will occur when a constant current is applied to the capacitor, but in a CR or RC circuit, the current is not constant; the current is set by the resistor, and depends on the voltage across the resistor according to Ohm's Law, and the voltage across the resistor is changing constantly as the capacitor charges or discharges; this causes the voltage to change with a non-linear, distinctive shape, called the RC curve (Google it) when charging or discharging is done through a resistor.

Last edited: Sep 30, 2014
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13. ### seymourfroggs

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Sep 29, 2014
So is this
I'm not trying to be funny, just trying to visualise it.
Where I was confused was being uncertain that when pin 3 goes + ve, pin 5 goes neg (for a while). Sometimes I understood that Pin 5 was also going + ve.
(Quoting fixed -- KrisBlueNZ)

Last edited by a moderator: Sep 30, 2014
14. ### KrisBlueNZSadly passed away in 2015

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No problem.
Pin 5 goes negative for a while when pin 3 changes from high to low. Because the capacitor is charged, with the pin 3 side more positive than the pin 5 side. So when pin 3 tries to go low, the capacitor "pushes" pin 5 below 0V and makes the input protection diode on pin 5 conduct.

This clamps pin 5 to about -0.7V (relative to the 0V rail) and this prevents pin 3 from falling straight down to 0V because pin 3 can only supply a limited amount of current - typically around 10 mA maximum - and the voltage across the capacitor changes at a rate that depends on the current (and the capacitance).

So the falling edge on pin 3 is not vertical; it doesn't jump straight from high to low. This will add some delay between the time when the input (on pin 2) goes high, until the second 4093 recognises a change from low to high on its input.

(BTW that signal from pin 3 of the first 4093 is being fed into pin 3 of the second 4093, which is an output, so there's a mistake there.)

15. ### seymourfroggs

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Sep 29, 2014
(BTW that signal from pin 3 of the first 4093 is being fed into pin 3 of the second 4093, which is an output, so there's a mistake there.)
Right. Should be Pin 2.

In the circuit as shown, the capacitor is between Pins 3 and 5. If the capacitor were between Pin 5 and ground, I presume Pin 5 value would still drop when Pin 3 did, but just not try to go negative(?). The time delay would be the same. The final Pin 10 output would still be a Positive signal (?).

I've viewed Google RC circuits and there does seem to be variation about exact placing.

16. ### KrisBlueNZSadly passed away in 2015

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There are two arrangements for a simple R-C circuit. Yours has an output feeding through a capacitor to an input, with a resistor from the input to a power supply rail. It's called an RC "differentiator".

The other arrangement has the capacitor and resistor exchanged; it is called an RC "integrator", and it produces a delay, rather than generating a pulse.

Draw up a schematic with two gates. Gate A's output goes through a resistor to gate B's input, and there is a capacitor from gate B's input to the 0V rail. Imagine gate A's output has been low for a long time, and the capacitor is discharged. So both sides of the resistor are at 0V.

Now imagine what will happen if gate A's output goes high and stays high. Remember my explanation of how a capacitor behaves, and remember how a resistor behaves. Where will current flow? What effect will the current flow have? What will happen to the voltage at gate B's input?

17. ### seymourfroggs

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Sep 29, 2014
Fantastic. Thanks.
Ans to §16: Current will go "slowly" to the capacitor and B will receive very little charge and so stay low for the RC time. Then B will go high. But voltage? Not sure. The voltage at the non-Ov side of the cap will be + ve and the same as for the voltage at B. Will that voltage try to draw - ve charge from B? Holding it low?

18. ### KrisBlueNZSadly passed away in 2015

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The capacitor is initially discharged, with no voltage across it. This can only change in response to current flowing into the capacitor.

When gate A's output ("A") goes high, the full supply voltage (well, almost) appears across the resistor, because one end is now high, and the other end is held low by the capacitor (remember, the voltage across the capacitor can't change instantly; it only changes at a RATE determined by the current flowing into it).

So current flows through the resistor according to Ohm's Law. If the power supply voltage is, say, 12V and the resistor is 47 kΩ, the initial current will be about 255 µA, and the capacitor will start to charge up, i.e. the voltage on the input of gate B ("B") will start to rise from 0V upwards towards the supply voltage.

Initially, when there is the full 12V across the resistor, and the full 255 µA flowing into the capacitor, the voltage across the capacitor (and therefore the voltage at "B") will increase according to dV / dT = I / C. With I = 255 µA and C = 15 nF, this works out to 17 V/ms, which means that after about 59 µs, the voltage will have risen by 1V.

Actually that's not exactly right, because as the voltage at B increases, the voltage remaining across the resistor drops, so the charging current drops. This leads to the distinctive exponential RC charge graph shape:

As the voltage at B gets closer to the supply voltage, the voltage remaining across the resistor gets closer to zero, and so does the charge current, and the slope of the line. But gate B will trigger around half way between 0V and the supply voltage (the threshold actually varies depending on the manufacturer of the IC, as well as manufacturing tolerances), so the duration of the delay is roughly predictable.

When the output of gate A goes low again, current flows through the resistor in the other direction, and the capacitor discharges back towards 0V.

Last edited: Oct 1, 2014
19. ### Laplace

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Apr 4, 2010
It is worth noting visually that the initial slope of an exponential charge curve will achieve the full value in just one time constant. Whereas the exponential curve takes about 5 time constants to reach full charge.

20. ### KrisBlueNZSadly passed away in 2015

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That's interesting! I didn't know that. No doubt there's a simple explanation. (I'm not asking you to give that explanation though.)