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RAM Address & data pin order

Discussion in 'Electronic Components' started by Googler, Jun 3, 2004.

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  1. Googler

    Googler Guest

    Hi ,
    In any datasheet of any parallel RAM/EPROM chip, the manufacturer labels
    the Address and Data pins ( D0, A0...A15 etc ).
    But it is not really necessary that we connect A0 of uP/uC to A0 of memory.
    ( as long as we are reading from the same location where we had stored the
    data, it should not matter to the uP/uC ).

    Then, why is it that memory manufacturers label the Address pins as A0...etc
    instead of just "Address pins" and Data pins as D0,D1..etc instead of
    I/O pins or data-pins ?

    does the label indicate their internal implimentation ?
    or is there something more to the labeling ?

    -Rgs
     
  2. JW

    JW Guest

    Nope. It just makes it easier on us poor technicians. I can only imagine
    what things would be like if everyone connected data lines and address
    lines randomly. (shudder)
     
  3. Mariano

    Mariano Guest

    I guess this could make sense in old DIP packaged EPROMS that you can
    program using memory programmers. You need to use the labeling to program
    the correct data in the IC. Other than this, I find it better to mix up
    address and data pins according to the PCB layout. And since generally you
    can program the memory using the uC/uP, there is no need of using memory
    programmers any more.

    Just a thought.
    Mariano
     
  4. Tim Wescott

    Tim Wescott Guest

    It makes a difference with PROM chips that will be programmed (they
    still need to be -- how does that microcontroller get it's boot code in
    the first place?). You can get around that if you know _how_ the
    addresses and data are mixed up, and make a program to preswizzle the
    information.

    It doesn't make a functional difference with asynchronous RAM.

    It _does_ make a difference with flash and EEPROM, because you generally
    erase those by sending "commands" -- usually by executing a sequence of
    writes to addresses 0x5555 and 0xaaaa. Swizzle the address and data
    spaces and this won't work, _and_ your memory blocks in your flash chips
    won't be contiguous anymore.

    It _does_ make a difference with synchronous dynamic RAM, where you have
    lines that pretend to be data and address but are really command and
    response lines, and where you want to do burst transfers.

    It _does_ make a difference with synchronous SRAM, but I've never used
    that so I don't know what it'll screw up beyond burst transfers.
     
  5. Googler

    Googler Guest

    Hi
    my question was WRT Async static RAM.
    due to cad layout consideration, we had to interchange some Data lines.
    but i wanted to know if the add/data line labeling had any deeper meaning
    in case of RAMs.

    it was interesting to know that interchanging lines would affect Sync-RAMs too.

    Thanks.
     
  6. The only time it's going to matter is when some poor tech hooks up a
    logic analyser and discovers "data corruption", so you might want to
    document it really well on the schematics and/or silk-screen something
    on the board...
     
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