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questions regarding vias

Discussion in 'Electronic Design' started by Michael Noone, Jan 18, 2006.

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  1. Vias are always an annoyance to me. Having no formal training in PCB
    layout, I'm always a little confused regarding them. Hopefully somebody
    here can help me out.

    First of all - I was wondering - how bad are vias? I mean I understand it's
    best to avoid them - but why? Production costs? Or do they add a
    significatn amount of capacitance or resistance to a trace? Most of the
    stuff I work at runs at about 5Mhz or under - at that speed should I be
    worrying about vias?

    Second of all - vias drill size and pad diameters always confused me. I've
    just been doing the smallest drill my board maker can do (about .4mm
    diameter) with a default pad size, which Cadsoft's Eagle has be double the
    drill (so .8mm). Is it really necessary for this pad to be so large? It
    makes layout with vias a bit of a nuisance.

    On a side note - did anybody here actually get formal training in PCB
    layout? I'm a 3rd year EE at UIUC and I have yet to see any PCB layout
    course, so I've been left wondering where people pick up this skill.

    Thanks for your help,

    -Mike
     
  2. Guest

    They're (a) a production cost, (b) two VERY SHARP bends in signal path.
    Probably not much of an issue at your frequencies, though.
    Vendor-dependent. What's your vendor's trace/space rule? The annulus
    surrounding the drill has to be this width or more.
    The big EDA companies run training programs. Many of our PCB guys are
    EEs who chose to go to PCB layout.
     
  3. linnix

    linnix Guest

    Expensive for small holes (<0.3mm).
    High impedence for high frequency (>100MHz).

    We have a board with 0.2mm holes and 0.2mm rings.
    But many rings and traces come out and the boards are trashed.
    Nope, but educated by the board makers with costs
    (very expensive to find out why boards are difficult to make and test).
    Ditto.
     
  4. (snip)
    When I pass significant current through a via (in contrast to to a
    signal voltage) I often up size the hole to lower the resistance of
    the via. I ask advice on such matters from the company producing the
    boards, or just guess. It depends on the board cost and volume (in
    other words, the risk of failure).
     
  5. Derek Potter

    Derek Potter Guest

    Things change in the PCB industry. many companies will give you
    unlimited vias at no extra cost. Vias used to be less reliable than
    solid copper traces but that's not an issue now.

    Of course a via does create a discontinuity in the transmission line
    but if you don't know about this then you probably don't know (and
    don't need to know) about other things that affect HF design.
    Your PCB vender will have design rules, typically .15mm for the copper
    width around a via, so you are fairly close to a standard size.
    However, it doesn't cost too much to go to 3 thou geometry, that's
    ..075mm, but in that case you'll be looking at .3mm holes or less.
    Practice.

    It's also important to find out about trace thicknesses for current
    capacity, layout considerations for EMC, good grounding techniques to
    minimize noise, the concept of current loops andf decoupling,
    different SMT footprints for different soldering methods, safety
    clearances etc. Fortunately all of these things are published on the
    Web.
     
  6. Derek Potter

    Derek Potter Guest

    There are actually tables for the current carrying capacity of vias. I
    can't recall the URL, but you can be sure it was only two clicks away
    from Google. You have to pull an acceptable temperature rise out of
    the air: some people panic over 5 degrees, others have a robust
    approach which regards 100 degrees as barely getting started :)
     
  7. I think there is also quite a bit of process variation from one vendor
    to another. Sometimes I am not worried about temperature rise as much
    as voltage drop. But that case is sometimes cured with a two trace
    approach, a big one to carry current and a small one to measure
    voltage at the beginning of the trace.
     
  8. wrote in
    Well production costs on my board are a non-issue, so it sounds like I
    probabaly don't have to worry too much about overusage of vias.
    I'm using Advanced Circuits, they say (https://www.33each.com/!
    33each1.asp):

    Min. 0.006" line/space
    Min. 0.015" hole size

    hence the .4mm drill (.015" = .381mm). .006" is .1524mm, so you think the
    ..2mm extra radius probabaly is pretty much unavoidable, right?
    It'd odd that schools don't offer it - seems like an oversight to me as PCB
    layout is fairly important.

    -Mike
     
  9. That's what I normally try to do. I normally try to have the diameter of
    the drill not too much smaller than the trace width, though by my intuition
    I'd think that you could get away with having the diameter a third of the
    trace width and still be golden (being that circumference is pi * d). By
    the way, did you recieve the updated layout that I sent you, and did you
    have any time to take a look at it? Thanks,

    -Mike
     
  10. in
    My board company is like this.

    I'm all too familiar with transmission lines (having just taken a class
    on them) - but I was unsure if information from that class would be
    pertinent to fairly low speed (5mhz) applications
    Unfortunately my board maker limites to just under .4mm holes.
    This is what I've been attempting to learn over the past couple of
    weeks, but my classes have been nearly useless in this regard and I have
    yet to find any good resources on the web.

    -Mike
     
  11. Rich Grise

    Rich Grise Guest

    I used to lay out with tape and peel-and-stick footprints, and one major
    reason to avoid vias is so you don't have to keep flipping that damn
    mylar over! And one major way to avoid (standalone) vias is to use the
    holes that are there anyway for components. :)

    As far as advice, look at how other people do it. Do as short and direct
    of power and ground as possible, and capacitate them well. Then, find
    the most direct paths, and use pencil. ;-) There used to be red and blue
    pencils, to do top and bottom on your paper layout - I guess these days
    the kids use computers to do that stuff. ;-)

    Good Luck!
    Rich
     
  12. Derek Potter

    Derek Potter Guest

    All voltages are between two points, not just one! My favourite
    subject to rant about is "earth" or "ground" which people take for
    granted for the same reason. Let's see now, Mr Customer, we have

    input signal ground
    output signal ground
    local circuit reference
    power return(s)
    RF ground (local)
    safety earth
    chassis
    ground plane
    IC/HF current return

    which one were you measuring "12V" with respect to?
     
  13. Derek Potter

    Derek Potter Guest

    Well, one way to look at it is this. The signal travels at ~ c/2 so it
    takes ~10ps to traverse a via. With a impedance mismatch ~ 100%,
    you're only going to get significant reflections on edges with that
    sort of rise time. Or sine waves >> 1GHz.

    You could also reckon on a mm or two of track having an inductance of
    point something nH, which immediately gives you the same time constant
    with a normal track impedance ~70.
    I do sympathise but you'll find it if you look, it's just that it will
    be in dribs and drabs as different people write from different
    perspectives.
     
  14. Michael Noone wrote:
    (snip)
    I did not receive it.
     
  15. That is very odd - It didn't bounce or anything. I'm not sure what
    happened. I just resent my previous e-mail. Can you confirm if you recieve
    it? Thanks again,

    -Mike
     
  16. Guest

    Hi Michael,

    Working with signals that are an order of magnitude faster (30-50MHz),
    I still don't worry about them.

    Working at /TWO/ orders of magnitude higher, I've had to characterize
    vias in terms of their effect on the stability of a canned RF
    transmitter IC, and it does have a significant effect there.
    I use AC all the time - my preferred PCB vendor.
    Looks like your minimum is very roughly 0.68mm outer diameter.
    #define RANT

    Jeez, you expected useful stuff to be taught at school? It would be a
    fundamental departure from college policies dating back several
    thousand years. A BSEE these days wastes twelve credits on Java
    programming. Sixteen credits are mathematics but half of this should
    have been taught in high school (and is, in other countries - US
    schools are too busy teaching that the world was created in seven days
    by God^H^H^Hperson or persons unknown, holding meetings to make sure
    that "students" are not singing Christmas carols). Credits wasted on
    liberal arts (exactly how is African-American history going to help you
    solve engineering problems?). Etc, etc.

    #undef RANT
     
  17. PeteS

    PeteS Guest

    When designing Infiniband boards (signalling rate up to 5Gb/s,
    depending on board), I had diff pairs (well, of course). It took some
    working out, but I made a calculator for my diff vias with sig gnd vias
    as a 4-inline set (gnd, sig, sig, gnd) so that the transition into the
    via was my only real discontinuity. The signal in the via (which is a
    significant distance with tr ~ 50ps) is actually in a transmission line
    (broadside coupled stripline, effectively).

    That was very effective in reducing my losses going from chip to
    connector, and chip to chip, to say nothing of helping EMC issues.

    General rule of thumb for most board fabs is drill >= board thickness /
    8, although you can get smaller (thickness / 10) if you are willing to
    accept lower yield (higher cost). The problem is the drill bits break
    quite frequently when the dia/depth ratio gets low. Certainly my mfrs
    would ask me if I really really needed vias 'that small'. For
    multilayer boards (significant number of layers - 8 or more, perhaps)
    with small annuli and small drills, registration becomes a problem for
    some mfrs as well.
    I sympathise as well. One might think that after all these years of
    'learning by experience' [i.e. learning from our mistakes] there aren't
    more resources to help others avoid those same mistakes. I'll be the
    first to admit good layout staff are difficult to come by.

    Cheers

    PeteS
     
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