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Discussion in 'Electronic Basics' started by adonis, Jun 4, 2007.

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  1. adonis

    adonis Guest

    picmicro 18f452 is a RISC family but it has 75 instruction set.why?
    does a RISC micro can have 75 instruction set?
  2. Don Bowey

    Don Bowey Guest
  3. Marra

    Marra Guest

    Some of the early PIC's did have very few instructions maybe thats why
    RISC has stuck ?

    They are great cheap microcontrollers, I have used them since 1985.
  4. Jasen

    Jasen Guest

    It's just hype from microchip, PICs aren't RISC, never were.

  5. Joel Kolstad

    Joel Kolstad Guest

    What's your definition of RISC?

    That was really the problem back in the '80s/'90s -- everyone was clammoring
    to tell you that "RISC is better!" and "we're RISC!" but, of course, there
    isn't any solid definition of what "RISC" and "CISC" were actually supposed to
    mean. How "reduced" is RISC? How "complex" is CISC?

    The textbook answer I know is basically... "something that looks like the
    original ARM CPUs -- pipelined, only load/save instructions can access memory
    directly, all other instructions use registers, of which there are lots" is

    With microcontrollers it's rather pointless to debate RISC vs. CISC anyway...
    with big-iron CPUs, the idea was that RISC let you ramp up the clock to a rate
    that more than made up for the "less complex instructions," under the
    assumption that both CPUs had access to the same fab and power consumption
    wasn't more or less equal. In a microcontroller, however, usually clock rate
    is limited far more by which silicon process the manufacturer really *does*
    have access to, power consumption, or other critieria. Indeed, for
    microcontrollers these days "work per joule" is probably one of the best
    metrics, as memory and clock cycles are both pretty cheap, but battery life

    (A good example here is the AVR vs. the MSP430... both are low-power, the AVR
    is RISCier and runs at a faster clock rate, but the MSP430 often performs
    better in benchmarks since it's actually a 16 bit CPU with a unified address
    space... although it costs more too...)

    ---Joel Kolstad
  6. Jasen

    Jasen Guest

    lots of registers,
    no single op-code read-modify-write (RAM).
    single-clock execution of most op-codes

    there's a wikipedia page that basically says the same thing too.

    This pic looks like an 8-bit processor like the 6800 or 6500 families with
    half the op-codes and some of the registers dropped and a harvard
    architecture bolted on. more of a sawnoff CISC than risc.

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