# Question in JFET pls

Discussion in 'General Electronics Discussion' started by samurad, Oct 22, 2012.

1. ### samurad

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Oct 22, 2012
hi all

i am a beginner , and i have question in JFET , as i understand that the current flow between drain and source by changing VDS ( Ohmic region ), utill it will reach max when VDS =VP then if we increased VDS more it will lead us to the saturation region , then if we want control the amount of the current we can do it by increase the reverse voltage on gate by increasing the -ve value of VGS and it will increase the width of the deplation to be max by more -ve value of VGS till it will be zero drain current

So , if it is right , it means the vlotage in the gate VGS is not the main reason for flowing current in the transitor , it just controlling it is amount

hence , how we can say it is Bias gate voltage ?? , Bias means it it the starting point and main cause to let the tranistor work and flow the current !!

pls i need clarification for this point , thanks

2. ### Harald KappModeratorModerator

10,768
2,425
Nov 17, 2011
The gate voltage controls the conductivity of the channel.
The current from source to drain is driven by the drain-source voltage.

Compare this to a switch:
You can open or close the switch (gate function), but current will only flow if a voltage cross the switch is present (source-drain function).

"Bias" hat nothing to do with aany "main cause to let the tranistor work and flow the current". Bias simply means to set the operating point.

Harald

3. ### samurad

2
0
Oct 22, 2012
thank you for your reply , so in JFET , the bias voltage is control the channel conductivity and drain current but the main source for thr current coming from VDS

But , in MOSFET , the current will start only if we applied positive voltage on the gate , +ve VGS (in N-Channel ) and then apply VDS because if we dont apply VDS no current will flow with VGS only , and then we can control the amount of the current by changing VDS (ohamic region) when VDS less than VGS , if i increased VDS to be equal to VGS we moved to saturation region then it will be control by VGS only , am i right ?

by the way , i tested it in this web site , pls clarify if i understood it wrongly

http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/mosfet.html

Thanks

Last edited: Oct 22, 2012
4. ### (*steve*)¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥdModerator

25,448
2,809
Jan 21, 2010
There are enhancement and depletion mode mosfets (see here). Note that this not an either/or situation, it is a continuum. For example the gate voltage that the device turns on can be made higher or lower (see logic level mosfets) and can essentially be made arbitrarily low. Continuing more in this direction you get a mosfet that is ON at a gate voltage of 0, and now we consider the gate voltage required to turn it off. And this too can be any value that the designer (of the mosfet) desires.

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