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Question about DRAM IC's

Discussion in 'Electronic Basics' started by Henry, Jun 30, 2006.

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  1. Henry

    Henry Guest

    I'm in the process of redesigning a RAM expansion board for an old Apple IIe
    series computer to help me better understand how electronics work. Some of
    you may remember the Apple IIe from back in the 80's. I've found it's a
    great platform to learn on. Anyway, the RAM expansion board uses 1 Meg x 1
    bit DRAM's and I want to modify the board to use 1 Meg x 4 bit DRAM's. Just
    a little homebrew project to further my knowledge of DRAM IC's and the
    circuits that drive them.

    Here's the datasheet for the 1 Meg x 1 bit DRAM's: Sheets/1Meg x 1bit DRAM.pdf

    Here's the datasheet for the 1 Meg x 4 bit DRAM's: Sheets/1Meg x 4bit DRAM.pdf

    A friend of mine has been helping me a bit along the way too. After we
    studied the two data sheets we noticed that the 4 bit DRAM has an Output
    Enable pin which the 1 bit DRAM does not. It would seen to me that if I
    invert the Write signal with a 74LS05 then I could use it to drive the
    Output Enable pin. So I wired the 74LS05 in to the circuit . I then wired
    up the rest of the signals accordingly. I took IO1 and connected it to
    where the first 1 bit DRAM I/O would be, IO2 and connected it to where the
    second 1 bit DRAM I/O would be, and so on. On my board the 1 bit DRAM's
    have pin 1 and 17 wired together. I then have the four remaining sockets in
    the bank of eight DRAM's filled with 1 bit DRAM IC's.

    Next I insert my board in to the computer, run my RAM test and... it fails.
    The program tests each DRAM separately, so the 1 bit DRAM's pass the test
    but the 4 bit DRAM fails. I've even tried several different brands of 4 bit
    DRAM's too. I can't seem to see a reason why it would fail, at least not
    according to the data sheets.

    Does anyone have any experience with what I'm doing or maybe can see
    something I'm missing from the data sheets? As you can probably guess I'm a
    little stumped and have been trying all sort of things for the past couple
    weeks. Any help would or guidance would be appreciated.


  2. Hello Henry,

    The x4 DRAM requires 1024 refresh cycles instead of 512.
    So this isn't a replacement, if you can't change the refresh to 1024
    cycles. Refresh means you have to cycle through all the 1024 lowest
    addresses every few milliseconds.

    Best regards,

  3. Hmm... Can't say too much without schematic but inverting /WR to achieve /OE
    may be too simple. Print out and compare the waveforms of the datasheets.
    There are a lot of possibilities and you need to know which ones are
    actually used. So what kind of read, write and refresh methods are
    implemented on the RAM-board? As for the refresh make sure the board
    provides a nine bits refresh address.

    petrus bitbyter
  4. Henry

    Henry Guest

    Hey guys. Thanks for the reply.

    petrus bitbyter: I did compare the waveforms of the datasheets and they do
    match up, or I should say they match to my eye. The board I'm working with
    is actually an expansion board to another card. I guess I'll have to draw
    the schematic to the main card to really understand how and what the main
    card is doing and what it expects from the daughter board. Thanks for the

    Helmut Sennewald: Concerning the refresh cycles - If I'm looking in the
    right place on the data sheets I see the 1bit DRAM requires 512 cycles every
    8 ms and the 4bit DRAM requires 1024 cycles every 16 ms. Isn't this the
    same thing or am I confusing something? Thanks.


  5. Hello Henry,

    512 refresh cycles mean you have to toggle through all the
    combinations(addresses) from ...0_0000_0000 to ...1_1111_1111
    within the refresh time.

    1024 refresh cycles mean you have to toggle through all the
    combinations(addresses) from ...00_0000_0000 to ...11_1111_1111
    within the refresh time.

    I remember that some computers did it in an interrupt loop.
    (It's a "dirty" solution.) Normally the DRAM controller
    performs the refresh cycles automatically uninfluential from the CPU.
    If a refresh occurs the cPU has to wait if it accesses the DRAM
    at the same time. Some older CPUs are so slow, that the DRAM
    controller may be able to perform two accesses within one CPU cycle.
    Then there is no extra delay penality for the CPU.

    The best solution is to find a 1M*4 DRAM with 512 refresh cycles.
    The type with 1024 refresh cycles can't be used if you haven't
    the possibility to increase the refresh to 1024 cycles.

    Best regards,
  6. Henry

    Henry Guest

    Hello again Helmut.
    Okay, I'll take a look around and see what's available. Thanks again for
    your time!

  7. The problem is that two lots of 512 cycles, do not activate the extra
    address line, that a '1024' cycle refresh implies...

    Best Wishes
  8. Henry

    Henry Guest

    Hello Roger.

    I'm not sure I understand what you mean about 'The problem is that two lots
    of 512 cycles, do not activate the extra address line, that a '1024' cycle
    refresh implies...'.

    Well, from what I believe is going on my card is set to refresh 512 address
    lines every 8 milliseconds - or at least that is what the data sheet for the
    1bit DRAM says it needs. Since the 1bit DRAM's work I will assume those are
    the numbers then. The DRAM I believe has a built in counter to advance the
    CAS address lines automatically from the LAST line it had accessed in
    refresh mode - so you don't need to apply all the possible address to the
    DRAM and eat up CPU time. Now if the DRAM is just idle and not being
    accessed then the current scheme will work just fine - i.e. - 512 refreshes
    in 8ms, 2 cycles of 512 = 1024 in 16ms. So that's good, or so I would

    Now what happens when the DRAM is at line 0 and the refresh kicks in? Of
    course it receive 512 cycles and the counter will now be on line 511. Now I
    access the DRAM in between the first 512 refresh and the second refresh and
    read or write data to line 0. The refresh then kicks in again after my read
    or write and advances the counter from the LAST line I accessed which was 0,
    to 511, thus missing the other 512 lines that still need to be refreshed.
    Now what if I access line 0 again just after that refresh and then the
    refresh kicks in again?

    I think this is what both of you have been talking about. Where if the
    board was designed to refresh 1024 times per refresh cycle then it's
    guarantied that every line of the array would be refreshed no matter what
    line in the array was last accessed. Am I following correctly?

    On another side test I tried a RAM board that used 256k x 1bit DRAM's. I
    replaced 4 of them with a 256k x 4bit DRAM. Same type of issue as with the
    1Meg DRAM's. Also the same refresh numbers issue as the 1 Meg DRAM's - that
    the 4bit DRAM refresh cycles are double that of the 1bit DRAM. It's the
    only thing that I can see is really that different between the two
    datasheets. In every case that I can see the 4bit DRAM specs are well
    within operating in a 1bit design - all but the refresh cycle numbers. As
    for the technical stuff, the 2 timing values that are relevant, that I see,
    are tCSR and tCHR. On the 1Mx1 chips, their min values are 10 and 15,
    respectively. With the 1Mx4 chips, I see 5 and 15. Looks to me that the
    1Mx4 chips are just as compatible (note: there's no value listed as in the
    max column for either chip). Even the tRPC value, which I'm not sure is a
    factor, is a min of 10 on the x1 and a 0 on the x4. The only real
    difference seems to be the refresh cycles which I now assume correspond
    directly to the memory array in the DRAM IC.

    I also believe my board to be doing /CAS-before-/RAS refresh but I can't say
    for sure. Any good 'test' to see if my assumption is correct? Wish I had a

    Any clarification to any of my thoughts/statements is always appreciated.

  9. Henry

    Henry Guest

    Well, I see I'm still not on the right track.

    I buddy of mine just sent me a .PDF about DRAM refresh. Here it is: Sheets/DRAM Refresh.pdf

    I'm under the assumption that my board uses CAS Before RAS refresh. After
    reading the data sheet I'm now guessing it doesn't. Now to buy a scope! ;-)

    Also after reading the data sheet I now have no idea what either Helmut or
    petrus bitbyter were trying to tell me when the mentioned the 1024 cycles
    issue. According to the data sheet IF my board is using CAS Before RAS
    refresh (or CBR) then as long as a refresh is done every 15.6us then I
    should be able to use ANY DRAM with the same requirements.

    So I'm basically as lost as I was before. :-( I think?

  10. Your first problem is that you've cross-posted to a slew of groups. I have
    very little desire to reply to some fool who feels they need to do that.

    But not only do you overly cross-post, but you lack comprehension.

    Inside the dynamic ram is an array of rows and columns. The refresh is
    to activate each location in turn, because dynamic memory is not static.
    It needs to be access in order to keep it's content. Since it's an array,
    you don't need to go through the full address space, just whatever is
    specified, the row or column.

    To use a simple example, say it's a really small RAM, 8 columns by 7 rows,
    ie 56 address locations. You have to refresh all those columns each time
    for a full refresh to happen. If you only had a counter with 7 bits
    output, one of those columns would never see a refresh, so a significant
    amount of the memory space would never be refreshed.

    So you get one of those new DRAMs with twice as much space, having 9 columns
    by 7 rows, all of 63 bits. Your old refresh circuit will no longer be good
    enough, because it has 8 outputs, but you now need 9 bits.

    That's what they are all trying to tell you as you spew this thread
    over a bunch of newsgroups.

    The details are specific to the DRAM. Some may require column refresh,
    some row refresh, and the arrangement of the array will vary. You have
    to track down the details and then match that.

  11. Eeyore

    Eeyore Guest

    Pardon ?

    Cross-posting to just *3 relevant groups* is the recommended practice. Far better
    than mutli-posting.

  12. Barbarian

    Barbarian Guest


    The problem may not relate to refresh...

    Think about where each of the Apple's raw address bits are going. Remember
    that some address bits are used as Row bits and some are used as Column

    The host system (Apple IIe?) controls how the bits are multiplexed... you
    can't just put chips with a different number of Row & Column bits than the
    system was designed for and expect it to work. (hint: Lost Address Bits)

  13. "Henry" <apl2research(.a.t.)> wrote in message

    Hi Henry,

    Good on you for keeping the side up, I too have enjoyed doing some of these
    things with some of the 80's computers.

    Type in "atari st 72-pin upgrade" into Google. Might help 1% maybe :)
    Mine is the only 72-pin hack out there for the ST :) I muddled through
    most of it so may not be as detailed in terms of RAS cycles and alike here.

    Hope to see you write up your experiences in the future.

    Best of luck,

  14. "Henry" <apl2research(.a.t.)> wrote in message


    Further to my post in the depths of the thread below, check this out too..

    Good luck! :)

  15. Henry

    Henry Guest

    Hey Alison.

    Thanks for the link. Funny how the SIMM worked with their system, but 4bit
    IC's don't seem to work with mine. I still have a couple tests I need to do
    though as I have had some new ideas since the last post.

    I also have purchased the DigiView logic analyzer. It should help me
    determine what is actually going on. Now I just need to sit down and
    continue my testing.

    Thanks again for the link!

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