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QFN footprint PCB layout

Discussion in 'Electronic Design' started by Fred, Sep 12, 2006.

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  1. Fred

    Fred Guest

    I have a QFN48 package and am wondering what's best for the ground pad
    underneath the chip. Are there any preferred layout patterns for this IC?
    I've done quite a lot of Googling but haven't come up with anything which
    seemed authoritative.
     
  2. PeteS

    PeteS Guest

    The best authority is the chip manufactuer, which you don't tell us.

    There are some app notes around for such things, but each device can
    have it's own characteristics.

    The pad may be there for thermal coupling, really low noise ground
    coupling, or both.

    Tell us what it is, we might be able to help.

    Cheers

    PeteS
     
  3. vasile

    vasile Guest


    Usualy the QFN or TQFN with exposed pad needs a multilayer ground
    with a large numbers of vias (15-20) between top and bottom side to
    evacuate the heat. Any evaluation kit from Maxim using QFN for example
    is showing how to do it.


    greetings,
    Vasile
     
  4. Copper the same size as the pad. Solder mask aperture the same size as the
    pad. Solder paste stencil aperture about 60% of the area of the pad, in
    order to not put too much paste on. If it is a small pad then just make a
    single aperture in the centre. If the pad is big then make multiple
    apertures in a windowpane pattern such that the total area is about 60% of
    the pad but no one aperture is too big.

    If the chip is big and power hungry and the pad is used as a heatsink then
    put lots of vias in it down to the groundplane. If not then just a few will
    do, if indeed it needs to be grounded (mostly they do).

    I think Xilinx has a reasonable app note on the subject.
     
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