Q on Transistor

Hi,

Is it possible to saturate the NPN BJT transistor in this biasing ?
Vcc
___
|
|
|
_| C
B |
---- Resistor ----|
|
-
| E
|---------------- Output
|
Resistor
|
|
|
---
- Ground


Since the transistor is OFF when '0' to base and hence output is '0'.
Then when '1' to base I would like to have 4.5V at the output, is that
possible to bias the transistor in saturation region (since Vce no
more <0.2V)?

 

Yes, if you drive it with a voltage at least one diode drop above Vcc.
Otherwise, it wont saturate, only clip.

Kevin Aylward

http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

 

Is "saturation" even meaningful in an emitter follower?

Thanks,
Rich

 

Sure. Saturation implies that the collector to emitter voltage is
less than the base to emitter voltage (the collector to base junction
becomes forward biased). If this circuit is driven with a voltage
more positive than the collector supply, the transistor may well
saturate.

 

Yup, "inverted state saturation". This can be very cool; if one were
to pull the left side of the resistor up above Vcc, the transistor
drop will go very low, like normal saturation. Pull up more, and it
can go to zero, and then *below* zero with the right transistor. I did
a 16-bit DAC once using discrete transistors and an R-2R wirewound
resistor network, with the base currents of the first few stages
tweaked for exactly zero saturation voltage.

John

 

OK, one more question.
If my transistor datasheet stated that the minimum hFE (DC current
transfer ratio) is 100 and the maximum is 400, can I still force this
transistor into saturation where hFE normally is 10 in saturated
transistor?

Thank you.

 

Yes. That beta spec applies only at some collector to emitter minimum
voltage and some maximum collector current. If the minimum collector
voltage is not met, the hfe falls dramatically, since it is reverse
bias across the collector to base junction that sweeps the charge
carriers injected into the base region by the emitter (perhaps I
should say, emitted by the emitter) efficiently to the collector (the
reverse bias collects those charges out of the reverse biased layer of
the base region). The base is called what it is because originally it
was the physical object that emitters and collectors were diffused
into from opposite sides.

Once the base voltage rises above the collector voltage, the base to
collector junction becomes forward biased, and base current diverts
directly to the collector (in addition to any feeble emitter charge
collection taking place). At some value of base collector forward
bias, the base to collector current must exceed the base to emitter
forward bias current, since there is no load resistor limiting this
current in the collector path. At that point, the hfe must be less
than 1.

 

Yup. If you jam in 1/10 as much base current as the load current, that
would be called a "forced beta" of 10.

But more base current doesn't always lead to lower saturation voltage.
For either the normal or inverted setup, there's some base current
that makes for the lowest Vce. A forced beta of 10 should be pretty
good, though.

John