R
Robert Baer
- Jan 1, 1970
- 0
Just assume two identical FETs in cascode configuration, with equal
value resistors in divider from top FET drain to gate, then to bottom
FET gate which is driven by an adjustable voltage.
Assume this is used as an adjustable shunt regulator in the zero to
15mA drain current region and the open circuit voltage from the supply
is more than twice the avalanche rating of the FETs.
Question: will any step change in the gate drive (bottom FET) cause a
large Vgs change in the top FET - sufficent to zap its gate?
If so, isn't it sufficent to mitigate the problem by using a G-S
capacitor (instead of a zener)?
Does the use of a FQD2N100 give more problems than use of a IRFBG20?
**
Useage: with opamp and load current monitor for forcing a settable
current thru load (the resulting voltage is read using a 10E9 resistor).
Very nice to measure points on high voltage zeners.
value resistors in divider from top FET drain to gate, then to bottom
FET gate which is driven by an adjustable voltage.
Assume this is used as an adjustable shunt regulator in the zero to
15mA drain current region and the open circuit voltage from the supply
is more than twice the avalanche rating of the FETs.
Question: will any step change in the gate drive (bottom FET) cause a
large Vgs change in the top FET - sufficent to zap its gate?
If so, isn't it sufficent to mitigate the problem by using a G-S
capacitor (instead of a zener)?
Does the use of a FQD2N100 give more problems than use of a IRFBG20?
**
Useage: with opamp and load current monitor for forcing a settable
current thru load (the resulting voltage is read using a 10E9 resistor).
Very nice to measure points on high voltage zeners.