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PWM Distortion

Discussion in 'Electronic Design' started by Andrew Holme, Nov 8, 2005.

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  1. Andrew Holme

    Andrew Holme Guest

    I'm investigating the intrinsic distortion of uniformly-sampled PWM as it
    affects the PFD output in a fractional-N synthesizer. One thing I've tried
    is to replace the complex MASH-generated divide-by-N sequence with a much
    simpler square wave. This is what the resulting PFD output spectrum looks
    like:

    http://www.holmea.demon.co.uk/Misc/PWM/1.gif

    The PWM sampling rate (reference/comparision frequency) was 512 and the
    square wave frequency was 64. You can see the fundamental and 3rd harmonics
    of the square wave, but there are also tones at the even-order harmonics
    which I think might be distortion products.

    What interests me is the way the amplitude of the even-order tones seems to
    increase with frequency. I thought the amplitude of an IMD product could
    only be proportional to a power of the input amplitude. I don't understand
    how it could also be proportional to frequency.

    When I run my simulation using the real MASH sequence, I get the PFD output
    spectrum I would expect, but there is a noise signal rising at 20 dB per
    decade superimposed on top of it: i.e. distortion with amplitude
    proportional to frequency.

    I don't know for sure if these tones are PWM distortion - maybe they're due
    to a loss of floating-point precision in my simulation; but I'm using the
    lcc-win32 C compiler because it has a "long double" type which supports the
    full 80-bit precision of the Intel FPU.

    Any pointers would, as ever, be appreciated ...

    TIA
    Andrew.
     
  2. No pointers, sorry. I was just wondering how Boki would have phrased
    you query :)


    martin
     
  3. Guest

    I don't know to what extent you are simulating a real circuit, but the
    even order products wouldn't necessarily have to be produced by
    "distortion" - whatever that might be in a switching circuit. I'd
    expect them to arise if the mark-to-space ration of the circuit moved
    away from exactly 50%.

    The obvious mechanism to generate th asymmetry is different propagation
    delays for the raisng and falling edges - which can be seen in real
    digital parts (and their data sheets).

    Because this differential delay is absolute, and pretty much
    independent of frequency, you'd expect the mark-to-space raito to get
    steadily worse as you raise the clock frequency.
     
  4. Mark

    Mark Guest

    I suggest you ask this question over at

    comp.dsp

    Mark
     
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