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pullup AND pulldown on a chip input

Discussion in 'Electronic Design' started by samiam, Mar 27, 2007.

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  1. samiam

    samiam Guest

    I just looked at a schematic I pulled off the net and I noticed that the
    Designer has a pullup resistor (to vcc) and a pulldown resistor (to
    ground) on the chip input.

    Exactly why is this done this way?

    I am used to seeing either one or the other.
    pullup for normally high
    pulldown for normally low

    Forgive me, I am a software guy who takes an interest in such things. Thanks
  2. Jim Thompson

    Jim Thompson Guest

    It's called CYA... after the thing is built clip off the wrong one ;-)

    ...Jim Thompson
  3. "samiam"
    What kind of chip? If it was an op-amp, then the resistors act as a voltage
    divider to set the input bias. Not sure why everyone here is assuming it to
    be a digital input. :-?
  4. Jim Thompson

    Jim Thompson Guest

    Good point. I've devised several chips now where one pin gives a
    select-one-of-three function...

    Tie High = Mode A
    Tie Low = Mode B
    Float = Mode C

    ...Jim Thompson
  5. John Larkin

    John Larkin Guest

    This is a "Thevenin termination". Using two resistors lets you nail
    both the pullup voltage and the line termination impedance at any
    values you like. The VME bus, among many others, uses this sort of

    Typical practice might be to have the high level be twice the nominal
    logic threshold or so, about 3 volts for VME, and the impedance
    whatever terminates best.

  6. samiam

    samiam Guest

    What kind of chip?

    a buffer/quickswitch

    I think I am partly to blame for that. I mentioned that I am a software
    guy by trade. My interest in this is purely with digital circuits.
  7. 2.2k used to be my favorite pullup resistor -- red-red-red.
  8. Hawker

    Hawker Guest

    There are three main reasons why pull up and pull down resistors are
    used that I can think of off the top of my head. They are

    1) To put a pin in a default state while items power up. For example you
    may want a processor to bring a pin high and another pin low on start up
    but for a few ms while a chip initializes the outputs may be inputs or
    high Z and not assert this. It prevents pin contention/latch up and
    other issues. For example you may want an output enable pulled high
    (off) and a external power supply pulled down (off).

    2) Stiff (under 2.21k) Pull ups are used to increase speed transitions
    at times. This is especially true with opto isolators and OC outputs
    (see below)

    3) Pull ups are used for open collector outputs for the VCC reference
    since by nature open collector cutouts have no voltage on them.

  9. Hawker

    Hawker Guest

    Oh I misread the request, sorry. I see on the same pin. Yes most likely
    that is what it is. Although it could also be termination. Was this a
    clock line. The two add up to make an impedance. If this is the case
    the values are usually odd ball and pull up and down are different values.

    Also - depending on what it drives the default state they may have
    wanted was in the middle. Not many real world uses for this, but there
    are some.

  10. Rich Grise

    Rich Grise Guest

    [Top-Post Repaired]
    I used to use 2.4K routinely, since the time a bag of about 1,000 of them
    fell out of the sky onto my desk. ;-)

  11. Rich Grise

    Rich Grise Guest

    What are the resistor values, and what chips are on either end of the

  12. Ban

    Ban Guest

    Yep, it is a termination for bus-lines used mostly on backplanes. The signal
    sees the parallel resistor value at the end of the line and doesn't get
    reflected. Whereas the driving current is only half of what it would be with
    a single resistor to gnd or Vcc.
    It makes only sense for CMOS, since these parts can source or sink the same
    A better way would be to create a middle voltage with a switching supply and
    terminate all lines with a single resistor to this. Now the dissipation is
    much lower, since we avoid the quiescent current in the dividers. There are
    ICs designed for this purpose.
    Some things have to be observed though. When no driver is active the middle
    voltage might cause excessive current in an activated input being in the
    linear region, so you have to stay above or below a bit. This will also give
    a defined output in this condition, all lines are low (or high), easily
    recognized by software.
  13. jasen

    jasen Guest

    eg MC140526 / SC41342 ?

  14. Jim Thompson

    Jim Thompson Guest

    Nope. The only standard product I've designed since 1970 have been
    ECL/PECL or LVDS. The parts with the three-way select were custom
    ASIC's, WiFi Repeater, GPS, etc. I've also used the scheme for
    production test... function not seen by ultimate user.

    ...Jim Thompson
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