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pull down on input of fpga i/o

Discussion in 'Electronic Design' started by panfilero, Sep 19, 2013.

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  1. panfilero

    panfilero Guest

    i need to interface to an fpga input, i have a 100k pull down there that gets tied to 3.3V for my logic high signal. it's been working fine, is a 100k pull down a pretty reasonable thing to do at an fpga input?
     
  2. There are a couple of considerations.. leakage current spec at maximum
    die temperature and potential noise pickup, so chip and
    application/layout dependent.

    Values in the range 4K7 to 20K are more common, and don't draw any
    more current if it's an input.
     
  3. Den torsdag den 19. september 2013 15.45.26 UTC+2 skrev panfilero:
    you have to look at the datasheet for the FPGA, a spartan6 pull up/down
    if enabled is 200-500uA at 3.3V, so an FPGA pullup would override an external
    100k pull down

    and depending on how you set a pin the pullups are enabled during configuration

    -Lasse
     
  4. kevin93

    kevin93 Guest

    100K sounds rather high, normally I would expect a lower value except if it is to reduce power consumption.

    Be careful of enabling bus-hold. That can make a mess of any passive pull-up or pull-down.

    Also at configuration time the FPGA may automatically enable a pull-up. That may cause confusion.

    kevin
     
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