pull down on input of fpga i/o

[panfilero]

i need to interface to an fpga input, i have a 100k pull down there that gets tied to 3.3V for my logic high signal. it's been working fine, is a 100k pull down a pretty reasonable thing to do at an fpga input?

 

[Spehro Pefhany]

i need to interface to an fpga input, i have a 100k pull down there that gets tied to 3.3V for my logic high signal. it's been working fine, is a 100k pull down a pretty reasonable thing to do at an fpga input?

There are a couple of considerations.. leakage current spec at maximum
die temperature and potential noise pickup, so chip and
application/layout dependent.

Values in the range 4K7 to 20K are more common, and don't draw any
more current if it's an input.

 

[Lasse Langwadt Christensen]

Den torsdag den 19. september 2013 15.45.26 UTC+2 skrev panfilero:

i need to interface to an fpga input, i have a 100k pull down there that gets tied to 3.3V for my logic high signal. it's been working fine, is a 100k pull down a pretty reasonable thing to do at an fpga input?

you have to look at the datasheet for the FPGA, a spartan6 pull up/down
if enabled is 200-500uA at 3.3V, so an FPGA pullup would override an external
100k pull down

and depending on how you set a pin the pullups are enabled during configuration

-Lasse

 

[kevin93]

i need to interface to an fpga input, i have a 100k pull down there that gets tied to 3.3V for my logic high signal. it's been working fine, is a 100k pull down a pretty reasonable thing to do at an fpga input?

100K sounds rather high, normally I would expect a lower value except if it is to reduce power consumption.

Be careful of enabling bus-hold. That can make a mess of any passive pull-up or pull-down.

Also at configuration time the FPGA may automatically enable a pull-up. That may cause confusion.

kevin