PSpice Output File Device

[Bob Penoyer]

Is there an output device that will allow a single circuit parameter
to be written to a file?

I know that VPWL_FILE can be used to read an ASCII file of two
columns, time and voltage.

 

[Jim Thompson]

Is there an output device that will allow a single circuit parameter
to be written to a file?

I know that VPWL_FILE can be used to read an ASCII file of two
columns, time and voltage.

The ".PRINT" statement can print-to-file most anything.

What did you have in mind? Your problem statement is somewhat muddy
;-)

...Jim Thompson

 

[Bob Penoyer]

The ".PRINT" statement can print-to-file most anything.

What did you have in mind? Your problem statement is somewhat muddy
;-)

I use Capture. How do I invoke the .PRINT statement?

I have a fairly large circuit that is having convergence problems. The
various parts ran all right when they were in their own projects. Now
the presence of a particular amplifier circuit has somehow affected
convergence in other parts of the overall circuit.

As one possible approach to this apparent dilema, I have considered
running the various sections separately so that one section's output
can be saved to a file and another section can read that file. That
way I hope to limit PSpice's computational load and maybe avoid the
convergence problem.

 

[Jim Thompson]

I use Capture.

Poor bastard ;-)

How do I invoke the .PRINT statement?

In PSpice Schematics it's just Get Part "Print1" or "PrintData", but I
couldn't find it in Capture.

You can also capture a PWL file directly from Probe by copying and
pasting into a text file, or Excel for that matter.

I have a fairly large circuit that is having convergence problems. The
various parts ran all right when they were in their own projects. Now
the presence of a particular amplifier circuit has somehow affected
convergence in other parts of the overall circuit.

Irrespective of what the Cadence types will tell you, set the
following:

ITL1=1500, ITL2=2000, ITL4=1000

Also set:

VNTOL=10uV
ABSTOL=10pA
RELTOL=0.01

Check the STEPGMIN box.

Might also try checking the SKIPBP box.

As one possible approach to this apparent dilema, I have considered
running the various sections separately so that one section's output
can be saved to a file and another section can read that file. That
way I hope to limit PSpice's computational load and maybe avoid the
convergence problem.

Sometimes that works. My general experience is that PSpice failing to
converge means you have a nearly unstable system.

...Jim Thompson

 

[Malcolm Reeves]

Sometimes that works. My general experience is that PSpice failing to
converge means you have a nearly unstable system.

Another approach to take is too look for daft signals. Large voltages
or currents etc. Then add some circuit parasitics to reduce these.
Convergence problems can be due to an unrealistic circuit, too simple
models. Sometimes just adding loads to batteries (i.e. increasing
standing current) can be enough to fix things.


--

Malcolm

Malcolm Reeves BSc CEng MIEE MIRSE, Full Circuit Ltd, Chippenham, UK
([email protected], [email protected] or [email protected]).
Design Service for Analogue/Digital H/W & S/W Railway Signalling and Power
electronics. More details plus freeware, Win95/98 DUN and Pspice tips, see:

http://www.fullcircuit.com or http://www.fullcircuit.co.uk

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