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Pspice CD4000 mixed signal design troubles me :-(

Discussion in 'CAD' started by Klaus Vestergaard Kragelund, Dec 28, 2003.

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  1. Hi

    Ok - so I'm going mad. It's been a long time since I last did Pspice (Orcad
    Capture 10.0) mixed analog/digital simulation.

    Theese two files show my schematics and the simulation results respectively:

    http://www.microdesign.dk/tmp/sch.jpg
    http://www.microdesign.dk/tmp/probe.jpg

    Why does the output of the CD4516 counter give only 2.6Volts on a 5Volt
    supply? I first suspected (still do) that somehow it doesn't get the correct
    supply and is fed througt protection diodes in the inputs. I have tried
    various things with the CD4000_pwr part and setting IPIN(VDD) parameters and
    much more. But now I'm stuck....

    Anyone see the obvious flaw?

    Thanks

    Klaus
     
  2. Jim Thompson

    Jim Thompson Guest

    Your biggest problem is that you are using Capture (gag me with a
    spoon :)

    Try creating a 5V DC supply. Label plus end as $G_CD4000_VDD and
    negative end as $G_CD4000_VSS. See if that makes it work.

    Also try making your load resistors larger and see if the levels
    increase.

    ...Jim Thompson
     
  3. Thanks for the suggestion. Just tried that - sorry to say - gives the same
    results:

    www.microdesign.dk/tmp/sch2.jpg
    www.microdesign.dk/tmp/probe2.jpg

    Can I somehow get what voltage the digital part "see" (by probing something
    like $G_CD4000_VDD or the IPIN(VDD) or something like that?)

    Cheers

    Klaus
     
  4. Jim Thompson

    Jim Thompson Guest

    In the library the values of $G_CD4000_V** should be shown... maybe
    it's 2.6V?

    A quick search for "*.lib" containing text "$G_CD4000_V" found a
    discussion in dig_io.lib that you should read.

    Also make sure that the libraries you have loaded don't conflict on
    the definition... IIRC the last loaded library dominates.

    Maybe Charlie Edmondson will weigh in, although Cadence may be closed
    until January 5, and he may not follow newsgroups from home.

    ...Jim Thompson
     
  5. I couldn't find where it said to be defined. But I found the dig_io.lib
    file, and that one specified 5.0V

    In this file they mention:

    Qoute:

    The default power supply voltage for TTL (and compatible CMOS) devices
    * is 5.0v.
    *
    * The CD4000 power supply voltage defaults to 5.0v. Its level is
    controlled
    * by two global parameters CD4000_VDD and CD4000_VSS. To use a different
    * power supply voltage, simply define the parameter CD4000_VDD in your
    * circuit, which will override the value defined below. For example,
    *
    * .PARAM CD4000_VDD = 12.0V
    *
    * will change the default voltage for all CD4000 devices to 12.0v.

    Unqoute

    So I added ".PARAM CD4000_VDD = 12.0V" to the circuit and now the output
    says 6.0V (half supply). Hmmmmmmm - at least that affected the
    value............

    I think I missing something essential like a digital ground or the
    like.......

    Cheers

    Klaus
     
  6. Jim Thompson

    Jim Thompson Guest

    It's probably because you're playing Eminem at the same time ;-)

    Looking at my schematics of digital things, I still used "AGND"
    without problem.

    ...Jim Thompson
     
  7. I solved it - nothing to do with supplies. An error (or not) in the model.
    The 4bit counter has four parallel load inputs to preset the counter. I had
    cleared those and never activated the parallel load pin. I had reset the
    device so I assumed (assumptions are the mother of all *****ups) the were
    cleared. But now I tried loading them with a zero nibble after I released
    the reset pin and that did the trick

    Thankyou very much for your time :)

    Klaus
     
  8. Jim Thompson

    Jim Thompson Guest

    On Sun, 28 Dec 2003 22:44:12 +0100, "Klaus Vestergaard Kragelund"

    [snip]
    All problems are simple, just bitchingly obscure ;-)

    ...Jim Thompson
     
  9. Active8

    Active8 Guest

    Problems are just opportunities, cleverly disuised as
    insurmountable obstacles. -Unknown
     
  10. Active8

    Active8 Guest

    Is he Edmonson Engr., Cadence, or both? Or maybe you mentioned he
    knew someone at Cadence.
     
  11. Jim Thompson

    Jim Thompson Guest

    Both.

    ...Jim Thompson
     
  12. Klaus,
    The problem was that the output was indeterminate. This translates to
    an analog level of half voltage... neither hi nor lo. When you found
    that you hadn't initialized the chip, then you found out why the outputs
    were indeterminate.

    This is one of the problems with simulation, sometimes things that work
    on the bench won't work in the sim because things that we take for
    granted aren't there. In this case, the output from any gate will be a
    definite state, and the logic will resolve itself on the bench. In the
    sim, we need to specify everything. People get upset if the sim makes
    too many assumptions about digital states... :cool:

    Thanks,
    Charlie
    Edmondson Engineering
    Unique Solutions to Unusual Problems

    PS. Cadence and most EDA firms do not maintain an official presence on
    Usenet. Too easily a magnet for flame wars and other bad things.
    Sometimes, you find someone who keeps an eye on things, or tries
    occasionally to be helpful, though...
     
  13. Yes, but the thing is the datasheet for the HEF4516
    (www.microdesign.dk/tmp/hef4516b.pdf) states:

    Qoute "A HIGH on MR resets the counter (O0 to O3 = LOW) independent of all
    other input conditions." Unqoute

    So I think the model is wrong since if I reset the device the outputs should
    go low and NOT indeterminate.

    Cheers

    Klaus
     
  14. Active8

    Active8 Guest

    Ah. Moonlighting's cool.
     
  15. John

    John Guest

    Happy new year to all.
    Don't know if this was solved but in PSpice/Schematics, you could solve this
    type of problem by going into Analysis Setup/Digital setup and initialise
    flip-flops to 1 or 0.

    regards,
    John
     
  16. Thanks for the tip John :)

    In Orcad 10 the place to find that is: -> Simulation Settings -> Options ->
    Category = Gate Level Simulation

    Cheers

    Klaus
     
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