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Discussion in 'General Electronics Discussion' started by elena_p, May 22, 2015.

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  1. elena_p

    elena_p

    6
    0
    May 22, 2015
    Hello! Is anyone here who know how to use Abel?Because i have to make an project (to implement a counter Gray with priority reset input). I've tried something but it doesn't work.
    Thanks!
     
  2. Harald Kapp

    Harald Kapp Moderator Moderator

    11,283
    2,583
    Nov 17, 2011
    Welcome to electronicspoint, Elena.

    Please show us your efforts so others can see where you may have failed. Use the Insert -> Code button on top of the edit box.
     
  3. elena_p

    elena_p

    6
    0
    May 22, 2015
    Code:
    MODULE counterGray
    
    TITLE 'NumaratorGraype5biti'
    
    declarations
    
    clock pin 1;
    clear pin 2;
    Y pin 3; "Y- control variable 1-up 0-down
    Q0,Q1,Q2,Q3,Q4 pin 15,16,17,18,19 istype 'reg';
    
    
    
    "state definitions
    
        QSTATE=[Q4,Q3,Q2,Q1,Q0];
        S0=[0,0,0,0,0];
        S1=[0,0,0,0,1];
        S2=[0,0,0,1,1];
        S3=[0,0,0,1,0];
        S4=[0,0,1,1,0];
        S5=[0,0,1,1,1];
        S6=[0,0,1,0,1];
        S7=[0,0,1,0,0];
        S8=[0,1,1,0,0];
        S9=[0,1,1,0,1];
        S10=[0,1,1,1,1];
        S11=[0,1,1,1,0];
        S12=[0,1,0,1,0];
        S13=[0,1,0,1,1];
        S14=[0,1,0,0,1];
        S15=[0,1,0,0,0];
        S16=[1,1,0,0,0];
        S17=[1,1,0,0,1];
        S18=[1,1,0,1,1];
        S19=[1,1,0,1,0];
        S20=[1,1,1,1,0];
        S21=[1,1,1,1,1];
        S22=[1,1,1,0,1];
        S23=[1,1,1,0,0];
        S24=[1,0,1,0,0];
        S25=[1,0,1,0,1];
        S26=[1,0,1,1,1];
        S27=[1,0,1,1,0];
        S28=[1,0,0,1,0];
        S29=[1,0,0,1,1];
        S30=[1,0,0,0,1];
        S31=[1,0,0,0,0];
       
    equations
        QSTATE.CLK=clock;
        QSTATE.AR=!clear;
    
    STATE_DIAGRAM QSTATE
    
        State S0:if Y then S1 else S31;
        State S1:if Y then S2 else S0;
        State S2:if Y then S3 else S1;
        State S3:if Y then S4 else S2;
        State S4:if Y then S5 else S3;
        State S5:if Y then S6 else S4;
        State S6:if Y then S7 else S5;
        State S7:if Y then S8 else S6;
        State S8:if Y then S9 else S7;
        State S9:if Y then S10 else S8;
        State S10:if Y then S11 else S9;
        State S11:if Y then S12 else S10;
        State S12:if Y then S13 else S11;
        State S13:if Y then S14 else S12;
        State S14:if Y then S15 else S13;
        State S15:if Y then S16 else S14;
        State S16:if Y then S17 else S15;
        State S17:if Y then S18 else S16;
        State S18:if Y then S19 else S17;
        State S19:if Y then S20 else S18;
        State S20:if Y then S21 else S19;
        State S21:if Y then S22 else S20;
        State S22:if Y then S23 else S21;
        State S23:if Y then S24 else S22;
        State S24:if Y then S25 else S23;
        State S25:if Y then S26 else S24;
        State S26:if Y then S27 else S25;
        State S27:if Y then S28 else S26;
        State S28:if Y then S29 else S27;
        State S29:if Y then S30 else S28;
        State S30:if Y then S31 else S29;
        State S31:if Y then S0 else S30;
    
    Test_Vectors  ([clock,clear,Y]->[Q4,Q3,Q2,Q1,Q0])
                   [.c., 0, .x.]->[0,0,0,0,0];
                   [.c., 1,  1 ]->[0,0,0,0,1];
                   [.c., 1,  1 ]->[0,0,0,1,1];
                   [.c., 1,  1 ]->[0,0,0,1,0];
                   [.c., 1,  1 ]->[0,0,1,1,0];
                   [.c., 1,  1 ]->[0,0,1,1,1];
                   [.c., 1,  1 ]->[0,0,1,0,1];
                   [.c., 1,  1 ]->[0,0,1,0,0];
                   [.c., 1,  1 ]->[0,1,1,0,0];
                   [.c., 1,  1 ]->[0,1,1,0,1];
                   [.c., 1,  1 ]->[0,1,1,1,1];
                   [.c., 1,  1 ]->[0,1,1,1,0];
                   [.c., 1,  1 ]->[0,1,0,1,0];
                   [.c., 1,  1 ]->[0,1,0,1,1];
                   [.c., 1,  1 ]->[0,1,0,0,1];
                   [.c., 1,  1 ]->[0,1,0,0,0];
                   [.c., 1,  1 ]->[1,1,0,0,0];
                   [.c., 1,  1 ]->[1,1,0,0,1];
                   [.c., 1,  1 ]->[1,1,0,1,1];
                   [.c., 1,  1 ]->[1,1,0,1,0];
                   [.c., 1,  1 ]->[1,1,1,1,0];
                   [.c., 1,  1 ]->[1,1,1,1,1];
                   [.c., 1,  1 ]->[1,1,1,0,1];
                   [.c., 1,  1 ]->[1,1,1,0,0];
                   [.c., 1,  1 ]->[1,0,1,0,0];
                   [.c., 1,  1 ]->[1,0,1,0,1];
                   [.c., 1,  1 ]->[1,0,1,1,1];
                   [.c., 1,  1 ]->[1,0,1,1,0];
                   [.c., 1,  1 ]->[1,0,0,1,0];
                   [.c., 1,  1 ]->[1,0,0,1,1];
                   [.c., 1,  1 ]->[1,0,0,0,1];
                   [.c., 1,  1 ]->[1,0,0,0,0];
    
    END
    
     
  4. elena_p

    elena_p

    6
    0
    May 22, 2015
    And this doesn't work :(



    Code:
    MODULE Counter _Gray
    
    TITLE 'Numarator_Gray_5_biti'
    
    declarations
    
    clock,reset pin 1,2;
    Y pin 3;
    Q0,Q1,Q2,Q3,Q4 pin 15,16,17,18,19 istype 'reg';
    
    "state declarations
    
        QSTATE=[Q4,Q3,Q2,Q1,Q0];
        S0=[0,0,0,0,0];
        S1=[0,0,0,0,1];
        S2=[0,0,0,1,1];
        S3=[0,0,0,1,0];
        S4=[0,0,1,1,0];
        S5=[0,0,1,1,1];
        S6=[0,0,1,0,1];
        S7=[0,0,1,0,0];
        S8=[0,1,1,0,0];
        S9=[0,1,1,0,1];
        S10=[0,1,1,1,1];
        S11=[0,1,1,1,0];
        S12=[0,1,0,1,0];
        S13=[0,1,0,1,1];
        S14=[0,1,0,0,1];
        S15=[0,1,0,0,0];
        S16=[1,1,0,0,0];
        S17=[1,1,0,0,1];
        S18=[1,1,0,1,1];
        S19=[1,1,0,1,0];
        S20=[1,1,1,1,0];
        S21=[1,1,1,1,1];
        S22=[1,1,1,0,1];
        S23=[1,1,1,0,0];
        S24=[1,0,1,0,0];
        S25=[1,0,1,0,1];
        S26=[1,0,1,1,1];
        S27=[1,0,1,1,0];
        S28=[1,0,0,1,0];
        S29=[1,0,0,1,1];
        S30=[1,0,0,0,1];
        S31=[1,0,0,0,0];
    
    equations
    
        QSTATE.clk=clock;
    
        when (Y) then {
                     when (reset) then QSTATE:=S0;
            else when (QSTATE==S0) THEN QSTATE:=S1;
            else when (QSTATE==S1) THEN QSTATE:=S2;
            else when (QSTATE==S2) THEN QSTATE:=S3;
            else when (QSTATE==S3) THEN QSTATE:=S4;
            else when (QSTATE==S4) THEN QSTATE:=S5;
            else when (QSTATE==S5) THEN QSTATE:=S6;
            else when (QSTATE==S6) THEN QSTATE:=S7;
            else when (QSTATE==S7) THEN QSTATE:=S8;
            else when (QSTATE==S8) THEN QSTATE:=S9;
            else when (QSTATE==S9) THEN QSTATE:=S10;
            else when (QSTATE==S10) THEN QSTATE:=S11;
            else when (QSTATE==S11) THEN QSTATE:=S12;
            else when (QSTATE==S12) THEN QSTATE:=S13;
            else when (QSTATE==S13) THEN QSTATE:=S14;
            else when (QSTATE==S14) THEN QSTATE:=S15;
            else when (QSTATE==S15) THEN QSTATE:=S16;
            else when (QSTATE==S16) THEN QSTATE:=S17;
            else when (QSTATE==S17) THEN QSTATE:=S18;
            else when (QSTATE==S18) THEN QSTATE:=S19;
            else when (QSTATE==S19) THEN QSTATE:=S20;
            else when (QSTATE==S20) THEN QSTATE:=S21;
            else when (QSTATE==S21) THEN QSTATE:=S22;
            else when (QSTATE==S22) THEN QSTATE:=S23;
            else when (QSTATE==S23) THEN QSTATE:=S24;
            else when (QSTATE==S24) THEN QSTATE:=S25;
            else when (QSTATE==S25) THEN QSTATE:=S26;
            else when (QSTATE==S26) THEN QSTATE:=S27;
            else when (QSTATE==S27) THEN QSTATE:=S28;
            else when (QSTATE==S28) THEN QSTATE:=S29;
            else when (QSTATE==S29) THEN QSTATE:=S30;
            else when (QSTATE==S30) THEN QSTATE:=S31;
            else when (QSTATE==S31) THEN QSTATE:=S0;
        }
        else
            QSTATE:=QSTATE;
    
    Test_Vectors  ([reset,clock,Y]->[Q4,Q3,Q2,Q1,Q0])
                   [0, .c., .x.]->[0,0,0,0,0];
                   [1, .c.,  1 ]->[0,0,0,0,1];
                   [1, .c.,  1 ]->[0,0,0,1,1];
                   [1, .c.,  1 ]->[0,0,0,1,0];
                   [1, .c.,  1 ]->[0,0,1,1,0];
                   [1, .c.,  1 ]->[0,0,1,1,1];
                   [1, .c.,  1 ]->[0,0,1,0,1];
                   [1, .c.,  1 ]->[0,0,1,0,0];
                   [1, .c.,  1 ]->[0,1,1,0,0];
                   [1, .c.,  1 ]->[0,1,1,0,1];
                   [1, .c.,  1 ]->[0,1,1,1,1];
                   [1, .c.,  1 ]->[0,1,1,1,0];
                   [1, .c.,  1 ]->[0,1,0,1,0];
                   [1, .c.,  1 ]->[0,1,0,1,1];
                   [1, .c.,  1 ]->[0,1,0,0,1];
                   [1, .c.,  1 ]->[0,1,0,0,0];
                   [1, .c.,  1 ]->[1,1,0,0,0];
                   [1, .c.,  1 ]->[1,1,0,0,1];
                   [1, .c.,  1 ]->[1,1,0,1,1];
                   [1, .c.,  1 ]->[1,1,0,1,0];
                   [1, .c.,  1 ]->[1,1,1,1,0];
                   [1, .c.,  1 ]->[1,1,1,1,1];
                   [1, .c.,  1 ]->[1,1,1,0,1];
                   [1, .c.,  1 ]->[1,1,1,0,0];
                   [1, .c.,  1 ]->[1,0,1,0,0];
                   [1, .c.,  1 ]->[1,0,1,0,1];
                   [1, .c.,  1 ]->[1,0,1,1,1];
                   [1, .c.,  1 ]->[1,0,1,1,0];
                   [1, .c.,  1 ]->[1,0,0,1,0];
                   [1, .c.,  1 ]->[1,0,0,1,1];
                   [1, .c.,  1 ]->[1,0,0,0,1];
                   [1, .c.,  1 ]->[1,0,0,0,0];
    
    END
    
     
  5. elena_p

    elena_p

    6
    0
    May 22, 2015
    I have to use GAL16V8
     
  6. elena_p

    elena_p

    6
    0
    May 22, 2015
    I've tried simulating the circuit on ISP lever Classic Project and doesn't work.:(
    I have the following errors:

    Input file: 'gray.tt2'
    Device 'p16v8'
    Note 4161: Using device architecture type P16V8R.
    Warning 4034:Unable to preserve preassignments - performing second pass without preassignments.
    Note 4059: Signal Q0 cannot be assigned (to pin 16) because
    there are too many terms for output Q0 pin 16.

    Note 4046: Signal Q1 (which has no OE) has been
    assigned to pin 15 (which has pin OE).
    Note 4046: Signal Q2 (which has no OE) has been
    assigned to pin 14 (which has pin OE).
    Note 4046: Signal Q3 (which has no OE) has been
    assigned to pin 13 (which has pin OE).
    Note 4046: Signal Q4 (which has no OE) has been
    assigned to pin 12 (which has pin OE).
    Design does NOT fit

    FIT complete. Time: 1 second.

    Done: failed with exit code: 0001.
     
  7. Harald Kapp

    Harald Kapp Moderator Moderator

    11,283
    2,583
    Nov 17, 2011
    Without knowing ABEL, I can tell that the issue is not an error in your ABEL program. The design is simply to big to fit in the GAL you want to use.
    To verify that the basic programming and the syntax are o.k., try a bigger GAL (just to test your program) or reduce the counter size from 5 bit to 4 bit to make it fit into the GAL 16V8. Once you have ensured the program is correct, I don't think you have many possibilities:
    • use a bigger GAL.
    • use two GALs and split the counter between them which will require conncting the inputs and outputs of the two GAls so each can know the state of the other.
      or
      use two GALS, one to count up, the other to count down and use a multiplexer to chose between the two.
    • try any optimizations that the compiler may offer.
     
  8. elena_p

    elena_p

    6
    0
    May 22, 2015
    GALp16v8 is the only GAL I should use . I tried to reduce and I have the same problem.
    I can use only a single GAL.
     
  9. Harald Kapp

    Harald Kapp Moderator Moderator

    11,283
    2,583
    Nov 17, 2011
    Sorry, I'm out of my wits then.
     
  10. Basha

    Basha

    1
    0
    Aug 29, 2016
    Hello anyone knows how to compile ABEL code please..?? I have ABEL code of cpld and need to simulate and get waveforms.
     
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