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programmable gain opamp

Discussion in 'Electronic Design' started by jutek, Mar 31, 2006.

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  1. jutek

    jutek Guest

    Hello

    I'm doing a programmable gain IC opamp. The gain is changeble through
    feedback resistors. I need 12 levels of gain. Normally it means 12
    resistors turning on/off by 12 mos transistors. It consists resistance
    divider with one constant resistor, and changes opamp's gain. But i
    can't let it to be 12 digital inputs, so a demux 12/1 with 4 addressing
    bits can be used. How can you judge this solution?
    I thought to make a resistors combination switch on by only 4
    transistors to avoid using a digital interface, to save some power, but
    i can't find resistrors values.

    I think these solutions can be wrong. I checked resistor's process and
    temperature dependence. It will be problem with gain accuracy when
    temperature changes. What can i do than?

    regards
     
  2. Tom Bruhns

    Tom Bruhns Guest

    Um, for one thing, the resistance of the MOSFETS may be an issue. It's
    not generally accurately spec'd and it has a much higher temp.
    coefficient than good resistors. Best to use them to switch so one tap
    on a series string of resistors connects the feedback to the inverting
    op amp terminal, so the feedback current is not in the FET. A
    one-of-many FET switch IC can be helpful: address inputs and an enable
    line do the decoding work for you. You may be able to find 1-of-16,
    and if not, two 1-of-8 switches would do. You may also find that a
    "digital pot" would work to get gains close enough for your
    requirements, and they generally have good temperature stability of the
    ratio.

    What temperature coefficient do you require? Use resistors which are
    appropriate for that. If it's for high volume production, get a custom
    resistive divider built; they can have very good ratio stability, even
    when the absolute resistances are not so stable. If it's for low
    volume, use resistors made by the same company, and if you can,
    resistors of the same value from the same batch. 0.1% 25ppm/C
    resistors are not terribly expensive these days. 1% 100ppm/C are
    almost dirt-cheap.
     
  3. Tom

    Tom Guest

    Jutek,
    In low-power integrated amplifier designs, you typically use switched
    capacitors instead of switched resistors for programmable gain. Which
    brings its own set of problems of course...

    A digital 4-to-12 decoder is a pretty basic circuit to draw from
    transistors and it consumes virtually no power. You can even use
    standard cells to design the digital bit if you want.

    greetings,
    Tom
     
  4. hello jutek,
    think about using a DA like DAC08 it is very easy and compact do do this.

    Marte
     
  5. hello jutek,
    Hint: AN-137 from www.analog.com

    Marte
     
  6. Ken Smith

    Ken Smith Guest

    Here's a 2 gain version:

    ---/\/\/---+---/\/\/---+---/\/\/-------------
    ! ! !
    ! ! SW1 !
    ! --O !
    ! <----!-\ !
    --------------O ! >--------
    !+/

    So long as the ratio of the resistors in constant and the op-amp is good
    enough, the gain does not drift.

    There is no current through SW1 so, within reason, its resistance doesn't
    matter. The feedthrough capacitances etc still matter however.

    If you can break your gain selections into 2 stages, you can save a lot of
    switches.
     
  7. jutek

    jutek Guest

    thanks a lot, but why do you say ther is no current through SW1?
     
  8. Jim Thompson

    Jim Thompson Guest

    The input to the OpAmp draws no (or insignificant) current.

    ...Jim Thompson
     
  9. jutek

    jutek Guest

    right

    and when we say about LDO?


    |\
    | \
    ref -|- \
    |--|+ /-----|out
    | | / |
    | |/ |
    | |
    | R2 R3 |
    |/\/\-/\/\--|
    | | |
    / | MOS |
    \
    R1/
    |
    |
    ___


    In this situation MOS conducts current. I think it should be in triode
    region to have small resistance, to not affect R3 resistance.
    I need a small quiescent current solution, cause whole LDO is specified
    for low power conditions.

    what can you suggest?

    regards
     
  10. jutek

    jutek Guest

    right

    and when we say about LDO?


    |\
    | \
    ref -|- \
    |--|+ /-----|out
    | | / |
    | |/ |
    | |
    | R2 R3 |
    |/\/\-/\/\--|
    | | |
    / | MOS |
    \
    R1/
    |
    |
    ___


    In this situation MOS conducts current. I think it should be in triode
    region to have small resistance, to not affect R3 resistance.
    I need a small quiescent current solution, cause whole LDO is specified
    for low power conditions.

    what can you suggest?

    regards
     
  11. Rich Grise

    Rich Grise Guest

    How about a multiplying DAC? Just use the top 4 bits, zero the others,
    and that will give you 16 gain levels, which, with a little scaling,
    you could work it so you only used 12.

    Good Luck!
    Rich
     
  12. Ken Smith

    Ken Smith Guest

    Why is the MOSFET where it is? Do you need to reverse bias it to turn it
    off? Can you afford the second fet needed to do the circuit I suggested?
     
  13. jutek

    jutek Guest

    it's there to switch on/off R3 resistance. If MOS is on, then it shorts R3

    and output voltage is set by R2/R1 ratio. When it's off, output is set
    by (R2+R3)/R1

    but when mos is on it consumes power and deteriorates overall quiescent
    current making it bigger
     
  14. Ken Smith

    Ken Smith Guest

    I don't think you understood my question, in the way I intended them.
    I've redrawn your schematic below with 2 different changes to it. Below
    each I explained what the reasoning is.
    \ -!!
    / !
    \ GND
    !
    GND

    The MOSFET needs to have its gate taken to a positive voltage with respect
    to its source and drain. Placing the MOSFET at the ground voltage makes
    more swing available and thus makes it easier to get a low on resistance.

    If you are only allowed one MOSFET and its on resistance is an issue, this
    circuit is worth considering.

    ! !
    !!---+-------!! !
    Control-------!! !!--------------- not(Control)
    !!--- --!! !

    This circuit requires that you have "control" and "not(Control)" so it
    requires that there be a logic inverter. It has huge advantages in the
    accuracy of the regulated voltage. There is (nearly) zero current in the
    MOSFET so its drop is near enough to zero that the offset voltage of the
    op-amp will be more.
     
  15. jutek

    jutek Guest

    in the case of first solution you gave me i think i can't use it cause
    resistors between + input and GND have to be quite large to minimize
    feedback current. I need 12 levels of output voltage, so 12 resistor
    would take a lot of area.

    The second solution is better. But as i wrote i need 12 output levels.
    it means 24 transistors to 12 inverters + 4to12 address decoder.
    transistors in the feedback circuit can affect frequency response due to
    capacity and its resistance.

    Is there a way to use less than 12 resistors +switches in the feedback?
    I thought about any combinations of resistors and only 4 switches
    without decoder. But i can't find exact resistors values.

    One more question. I need the change from the lowest programmed output
    to the highest one should be as fast as possible. What this time is
    related to? I didn't find any articles about adjustable LDO design.
    When i simulate LDO without digital interface and programmable resistors
    everything is ok, but when i use switch, to turn on/off a resistor,
    output's voltage settling time is very long. Dou you know how to
    decrease it?

    regards
     
  16. Ken Smith

    Ken Smith Guest

    Are these 12 levels following any simple rule we could take advantage of?

    If there are 12 levels, you need 12 transistors. Only one transistor is
    on and all the others are off. If you already have 12 decoded lines. you
    likely already have the gate drive signals. My solution was for the 2
    value case where the decoder becomes an inverter.

    To make the transient responce good, chances are you will want to hook
    some capacitance directly from the op-amps output to its inverting input.
    What are the levels you need to make? What is the reference.
    "as fast as possible" is quite a requirement. It is unlikely that you
    will get under 1pS rise time in a low current device :> :>

    The time to get from one voltage to another is inversely proportional to
    the bandwidth, all else being equal.

    You are trying to get low current this usually implies a low bandwidth.
    You need to find out what the real limits are for the spec.

    Adding a feedforward path to the design may help. Basically, you make the
    circuit get close the right value quickly but inexactly and then the servo
    pulls it to the exact value. This may be getting beyond the scope of the
    question here.

    I didn't find any articles about adjustable LDO design.
    If I knew what you wer really doing, I might be able to come up with
    something. As it is, I'll guess that you haven't considered all the
    effects of the capacitances of the MOSFETs.
     
  17. jutek

    jutek Guest

    outputs are from 1 to 1.6 with 50mV step. vref is 1

    the resistors are 0-120k with 10k step

    first i simulated LDO without these resistors, choosing one them step
    by step. transient response of the LDO was good. i mean, response for
    the change in load current. settling time and load regulation was ok. So
    i think the badwidth was enough. but when i added 10k and 110k
    resistors + one switch and simulated change in the output from 1.05 to
    1.6 the settling time was awful. I need 1us and there was much more.
     
  18. Ken Smith

    Ken Smith Guest

    outputs are from 1 to 1.6 with 50mV step. vref is 1

    the resistors are 0-120k with 10k step[/QUOTE]

    I think you can cut down on the resistors and MOSFETs very easily at the
    cost of a second op-amp.

    Without the second op-amp but allowing for some error due to MOSFET
    resistance:


    1V ---------------!+\
    ! >----+----------
    ---!-/ !
    ! !
    ---+---++--+-/\/\---
    ! ! ! ! NR
    / / / /
    R \ \ \ \ 8R
    / / / /
    ! ! ! !
    MOS MOS MOS MOS
    ! ! ! !
    GND GND GND GND

    Since your voltages step off uniformly, you can use binary weighted
    resistors to both decode a 4 bit number and control the output.

    Now the "N" of "NR" needs to be found. Just to be clear what I mean, I'm
    going to go through the thinking in baby steps. It is also useful for
    making sure I have it right.

    When 8R is on, 8R has 1V on it and NR has 0.05V on it. We can assume that
    no current flows into the op-amp so the "NR" has the same current as the
    "8R"

    1V = 8R * I

    0.05V = NR * I

    Solve each for I

    1V/8R = I ( divided both sides by 8R )


    0.05V/(NR) = I ( divided by NR )


    Since it is the same I in both equations we can say this:


    1V/8R = 0.05V/(NR)

    Now we find "N":

    1V * N / 8 = 0.05V (Mult by NR)


    N / 8 = 0.05 (Div by 1V)

    N = 8 * 0.05 (Mult by 8)

    N = 0.40


    Now we have a value for N, we can go back and work out what we want R to
    be.


    Did you use the MOSFET as a switch or did you use a "switch" in your
    model? If you used the MOSFET, the capacitances of the MOSFET are likely
    to be the problem.

    You may have been fooled by the load regulation, into thinking something
    that isn't true. Since I don't know the details you your op-amp, I will
    assume something just for my explaination. I will say that internally,
    your op-amp looks like this:



    Vcc
    ! Vcc
    \ !
    /R1 \R3
    \ /
    ! \
    ---+--- ! Vcc
    pnp ! ! pnp ----+ !
    !/e e\! ! ! !/ Q4
    -in ---! !--+in --- +-----! npn
    !\ /! C1 --- ! !\e
    ! ! X! !/ -------- Out
    GND +-------------+--! Q3
    ! !\e
    \ npn !
    / GND
    \R2
    !
    GND


    Since this is a low power op-amp, lets assume that all of these
    transistors cut off at 100KHz. That is, we are going to take the *bogus*
    assumption that the collector current lags the E-B voltage by 45 degrees
    at 100KHz and there is no other capacitances in the circuit except for C1.

    If there is a sudden step on the output, it shows up right away on the E-B
    voltage of Q4, so the current output starts off changing at a rate
    controlled only by the 100KHz speed of Q4. After a while, the change in
    output voltage makes it through your resistors to the (-in) input of the
    op-amp, through all the parts to the base voltage of Q4. This means that
    the change in current will look like this:

    ...............................***
    .........................*********
    ...................******.........
    .............******...............
    ........*****.....................
    .......*..........................
    ......*...........................
    .....*............................
    ....*.............................
    ...*..............................
    **...............................
    ! ! !
    ! "Fast rise" Slowly
    ! Because of we get the
    ! Q4 alone rest of the
    ! way there
    Step applied


    The the shape you get if you suddenly change the divider feeding the (-in)
    point will be quite different. In that case, it will only have the slower
    second part.

    There is an alternative version of this circuit were "X" is grounded
    rather than run to the base of Q3. If you disconnect that point from
    ground and hook it to some other low impedance point, it can provide you
    with an easy way to add feedforward to the design.

    Do your control lines come from some sort of bufferes so that you can be
    sure of their amplitude and are very clean?
     
  19. jutek

    jutek Guest

    thanks for the circuit and clear explanation
    i use MOSFET as a switch
    so it would seem the load current change response mixed me up. i didn't
    thought the bandwidth has to bo so wider for change in the programmed
    output response than for step load current one.


    Since I don't know the details you your op-amp, I will
    I tried a few opamps topologies mostly one stage ones. I use CMOS
    technology.
    i will add it when necessary.

    thanks again and best regards
     
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