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Procedural Assignment error (verilog )

Discussion in 'General Electronics Discussion' started by vead, Sep 23, 2014.

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  1. vead

    vead

    473
    14
    Nov 27, 2011
    when i compile code I am getting following error
    line if (ld==1) q4 <= d4;

    Error (10137): Verilog HDL Procedural Assignment error at core_v.v(70): object "q4" on left-hand side of assignment must have a variable data type
    Code:
    module core_v(clk,ld,d0, q0,d1,d2,q1,q2,a,b,z,sel,d,q,d3,q3,d4,q4 );
    
    input clk;
    input ld;
    reg [3:0] q0;
    reg [3:0] q1;
    reg [3:0] q2;
    reg [3:0] z;
    
     
    
    //add r0
    core_v core_vr0 ( d0, q0);
            input  [3:0] d0;
            output q0;
            always @(posedge clk)
            begin
               if (ld==1) q0 <= d0;
               end
        
    
    // add r1
            core_v core_vr1 ( d1, q1);
            input  d1;
            output q1;
            always @(posedge clk)
            begin
               if (ld==1) q1 <= d1;
            end
    
    //add r2
    core_v core_vr2_i ( d2, q2);
            input  d2;
            output  q2;
           
            always @(posedge clk)
            begin
               if (ld==1) q2 <= d2;
          
            end
    
    // add acc
    core_v core_vacc( d, q);
            input  d;
            output q;
             reg [3:0] q;
            always @(posedge clk)
            begin
               if (ld==1) q <= d;
            end
    
    //add temacc   
    core_v core_tempacc(d3,q3 );
            input  d3;
            output q3;
            always @(posedge clk)
            begin
             if (ld==1) q <= d;
             end
         
    
    // add accreg   
    core_v core_tempreg(clk, ld, d4, q4);
            input  d4;
            output q4;
           
            always @(posedge clk)
            begin
               if (ld==1) q4 <= d4;
            end
        
    //add alu  
    core_v core_alu (z,a,b,sel);
    input a, b;
    input sel;
    output z;
    
    [email protected](sel,a,b)
    begin
    case(sel)
    4'b0000: z=a+b;
    4'b0001: z=a-b;
    4'b0010: z=b-1;
    4'b0011: z=a*b;
    4'b0100: z=a&&b;
    4'b0101: z=a||b;
    4'b0110: z=!a;
    4'b0111: z=~a;
    4'b1000: z=a&b;
    4'b1001: z=a|b;
    4'b1010: z=a^b;
    4'b1011: z=a<<1;
    4'b1100: z=a>>1;
    4'b1101: z=a+1;
    4'b1110: z=a-1;
    endcase
    end
    endmodule 
    how to remove this error
     
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